/freebsd-10.0-release/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/aggs/ |
H A D | tst.signedkeyspos.d | 66 @i16["mouse", (short)-2] = sum(-2); 67 @i16["dog", (short)-2] = sum(-22); 68 @i16["cat", (short)-2] = sum(-222); 69 @i16["mouse", (short)-1] = sum(-1); 70 @i16["dog", (short)-1] = sum(-11); 71 @i16["cat", (short)-1] = sum(-111); 72 @i16["mouse", (short)0] = sum(0); 73 @i16["dog", (short)0] = sum(10); 74 @i16["cat", (short)0] = sum(100); 75 @i16["mous [all...] |
H A D | tst.signedkeys.d | 101 @i16[(short)-2] = sum(-2); 102 @i16[(short)-1] = sum(-1); 103 @i16[(short)0] = sum(0); 104 @i16[(short)1] = sum(1); 105 @i16[(short)2] = sum(2);
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/freebsd-10.0-release/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 267 MVT::i16, AM.Disp, 270 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16, 273 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/); 275 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/); 280 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i16); 316 case MVT::i16: 341 case MVT::i16: 349 VT, MVT::i16, MVT::Other, 364 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8); 370 VT, MVT::i16, MV [all...] |
H A D | MSP430ISelLowering.cpp | 68 addRegisterClass(MVT::i16, &MSP430::GR16RegClass); 84 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); 90 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); 93 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 98 setOperationAction(ISD::SRA, MVT::i16, Custom); 99 setOperationAction(ISD::SHL, MVT::i16, Custom); 100 setOperationAction(ISD::SRL, MVT::i16, Custom); 103 setOperationAction(ISD::ROTL, MVT::i16, Expand); 104 setOperationAction(ISD::ROTR, MVT::i16, Expand); 105 setOperationAction(ISD::GlobalAddress, MVT::i16, Custo [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 232 case MVT::i16: 261 case MVT::i16: 291 case MVT::i16: 314 case MVT::i16: 343 case MVT::i16: 366 case MVT::i16: 473 case MVT::i16: 497 case MVT::i16: 527 case MVT::i16: 551 case MVT::i16 [all...] |
H A D | NVPTXISelLowering.cpp | 94 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass); 106 setOperationAction(ISD::BR_CC, MVT::i16, Expand); 111 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 130 setOperationAction(ISD::ROTL, MVT::i16, Expand); 131 setOperationAction(ISD::ROTR, MVT::i16, Expand); 134 setOperationAction(ISD::BSWAP, MVT::i16, Expand); 163 setTruncStoreAction(MVT::i16, MVT::i1, Expand); 931 // stored type to i16 and propogate the "real" type as the memory type. 960 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal); 1483 // loaded type to i16 an [all...] |
/freebsd-10.0-release/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/typedef/ |
H A D | tst.TypedefDataAssign.d | 85 new_int16 i16;
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/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 303 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 }, 304 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 }, 305 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 }, 306 { ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 }, 335 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 }, 336 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 }, 337 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 }, 338 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 }, 360 // i16 -> i64 requires two dependent operations. 361 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, [all...] |
H A D | ARMSelectionDAGInfo.cpp | 98 VT = MVT::i16; 121 VT = MVT::i16;
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H A D | ARMFastISel.cpp | 560 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1) 784 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) 909 case MVT::i16: 1030 case MVT::i16: 1154 case MVT::i16: 1421 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || 1457 case MVT::i16: 1484 // We have i1, i8, or i16, we need to either zero extend or sign extend. 1600 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) 1607 if (SrcVT == MVT::i16 || SrcV [all...] |
/freebsd-10.0-release/sys/contrib/octeon-sdk/ |
H A D | cvmx-fau.h | 301 uint64_t i16; member in union:__anon6872 304 result.i16 = cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value));
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/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | ValueTypes.h | 45 i16 = 3, // This is a 16 bit integer value enumerator in enum:llvm::MVT::SimpleValueType 76 v1i16 = 25, // 1 x i16 77 v2i16 = 26, // 2 x i16 78 v4i16 = 27, // 4 x i16 79 v8i16 = 28, // 8 x i16 80 v16i16 = 29, // 16 x i16 81 v32i16 = 30, // 32 x i16 279 case v32i16: return i16; 362 case i16 : 468 return MVT::i16; [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 106 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) { 144 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) { 219 LocVT == MVT::i16) { 607 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 855 if (RegVT == MVT::i8 || RegVT == MVT::i16 || 1152 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote); 1153 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); 1154 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote); 1155 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); 1289 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Lega [all...] |
H A D | HexagonVarargsCallingConvention.h | 49 LocVT == MVT::i16 ||
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/freebsd-10.0-release/contrib/llvm/include/llvm/Support/ |
H A D | DataTypes.h.in | 140 # define INT16_C(C) C##i16
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/freebsd-10.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.cpp | 95 AVT = MVT::i16; 217 AVT = MVT::i16;
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H A D | X86ISelDAGToDAG.cpp | 616 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); 619 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); 1316 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); 1318 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); 1672 // A special case for i16, which needs truncating as, in most cases, it's 1675 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 && 1736 case MVT::i16: 1874 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 && 1938 if (LdVT == MVT::i16) return X86::DEC16m; 1944 if (LdVT == MVT::i16) retur [all...] |
H A D | X86FastISel.cpp | 194 case MVT::i16: 256 case MVT::i16: Opc = X86::MOV16mr; break; 300 case MVT::i16: Opc = X86::MOV16mi; break; 781 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16) 868 case MVT::i16: return X86::CMP16rr; 886 case MVT::i16: return X86::CMP16ri; 1127 case MVT::i16: TestOpc = X86::TEST16ri; break; 1237 const static unsigned NumTypes = 4; // i8, i16, i32, i64 1280 }, // i16 1305 case MVT::i16 [all...] |
H A D | X86AsmPrinter.cpp | 247 ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8)); 391 Reg = getX86SubSuperRegister(Reg, MVT::i16);
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H A D | X86ISelLowering.cpp | 189 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 250 addRegisterClass(MVT::i16, &X86::GR16RegClass); 259 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 261 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 263 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 277 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 297 // SSE has no i16 to fp conversion, only i32 299 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 303 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 307 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promot [all...] |
/freebsd-10.0-release/sys/cddl/contrib/opensolaris/uts/common/os/ |
H A D | fm.c | 230 uint16_t i16; local 267 (void) nvpair_value_int16(nvp, (void *)&i16); 268 c = fm_printf(d + 1, c, cols, "%x", i16); 272 (void) nvpair_value_uint16(nvp, &i16); 273 c = fm_printf(d + 1, c, cols, "%x", i16);
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/freebsd-10.0-release/contrib/llvm/lib/IR/ |
H A D | ValueTypes.cpp | 117 case MVT::i16: return "i16"; 183 case MVT::i16: return Type::getInt16Ty(Context);
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/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 1056 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); 1062 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; 1068 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); 1073 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; 1090 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); 1096 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break; 1102 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && 1108 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
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/freebsd-10.0-release/contrib/llvm/lib/Target/R600/ |
H A D | AMDILISelLowering.cpp | 45 (int)MVT::i16, 64 (int)MVT::i16, 303 } else if (OVT.getScalarType() == MVT::i16 320 } else if (OVT.getScalarType() == MVT::i16) {
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/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 1180 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break; 1189 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; 1198 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; 1207 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; 1216 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; 1225 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; 1234 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; 1243 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; 1976 if (VT == MVT::i16) 2039 if (VT == MVT::i16) [all...] |