/freebsd-10.0-release/contrib/llvm/lib/CodeGen/ |
H A D | AllocationOrder.cpp | 35 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
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H A D | RegAllocBase.cpp | 101 << MRI->getRegClass(VirtReg->reg)->getName() 122 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
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H A D | PeepholeOptimizer.cpp | 164 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); 175 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0; 269 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); 363 if (MRI->getRegClass(SrcSrc) != MRI->getRegClass(Def))
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H A D | VirtRegMap.cpp | 102 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); 123 << MRI->getRegClass(Reg)->getName() << "\n"; 131 << "] " << MRI->getRegClass(Reg)->getName() << "\n";
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H A D | TargetRegisterInfo.cpp | 87 const TargetRegisterClass *SubRC = getRegClass(Idx + Offset); 156 return TRI->getRegClass(I + CountTrailingZeros_32(Common));
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H A D | MachineSink.cpp | 135 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); 136 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); 506 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg)))
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H A D | OptimizePHIs.cpp | 168 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
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H A D | Spiller.cpp | 88 const TargetRegisterClass *trc = mri->getRegClass(li->reg);
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H A D | TargetInstrInfo.cpp | 39 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, function in class:TargetInstrInfo 54 return TRI->getRegClass(RegClass); 326 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); 331 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
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H A D | LiveRangeEdit.cpp | 35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); 384 << MRI.getRegClass(LI.reg)->getName() << '\n');
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H A D | MachineRegisterInfo.cpp | 50 const TargetRegisterClass *OldRC = getRegClass(Reg); 65 const TargetRegisterClass *OldRC = getRegClass(Reg);
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H A D | CalcSpillWeights.cpp | 79 const TargetRegisterClass *rc = mri.getRegClass(reg);
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H A D | RegisterPressure.cpp | 52 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 68 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 112 const TargetRegisterClass *RC = MRI->getRegClass(Regs[I]); 129 const TargetRegisterClass *RC = MRI->getRegClass(Regs[I]);
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H A D | TailDuplication.cpp | 285 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) { 396 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); 433 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 443 MRI->constrainRegClass(VI->second, MRI->getRegClass(Reg));
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H A D | UnreachableBlockElim.cpp | 201 MRI.constrainRegClass(Input, MRI.getRegClass(Output));
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H A D | RegisterCoalescer.cpp | 283 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src)); 286 } else if (!MRI.getRegClass(Src)->contains(Dst)) { 291 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); 292 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); 650 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg))) 769 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI, *MF); 2179 << MRI->getRegClass(Reg)->getName() << '\n');
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H A D | InlineSpiller.cpp | 726 MRI.getRegClass(SVI.SpillReg), &TRI); 1084 MRI.getRegClass(NewLI.reg), &TRI); 1102 MRI.getRegClass(NewLI.reg), &TRI); 1231 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original)); 1282 << MRI.getRegClass(edit.getReg())->getName()
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H A D | RegAllocGreedy.cpp | 553 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) < 554 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg))); 643 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg); 986 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); 1253 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); 1304 if (!RegClassInfo.isProperSubClass(MRI->getRegClass(VirtReg.reg)))
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/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 146 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); 283 MRI->getRegClass(MI->getOperand(1).getReg()); 284 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { 541 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass)) { 557 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { 563 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
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/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); 161 DstRC = MRI->getRegClass(VRBase); 220 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); 238 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 319 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); 426 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); 485 TRC == MRI->getRegClass(SrcReg)) { 536 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) 577 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); 594 const TargetRegisterClass *RC = TRI->getRegClass(DstRCId [all...] |
/freebsd-10.0-release/contrib/llvm/utils/TableGen/ |
H A D | CodeGenTarget.h | 125 return *getRegBank().getRegClass(R);
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/freebsd-10.0-release/contrib/llvm/include/llvm/MC/ |
H A D | MCRegisterInfo.h | 383 const MCRegisterClass& getRegClass(unsigned i) const {
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/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 249 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
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/freebsd-10.0-release/contrib/llvm/lib/Target/R600/ |
H A D | AMDGPUInstrInfo.cpp | 258 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());
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/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 446 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 480 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 510 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || 511 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { 513 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
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