/freebsd-10.0-release/contrib/llvm/lib/Target/X86/InstPrinter/ |
H A D | X86InstComments.cpp | 38 DestName = getRegName(MI->getOperand(0).getReg()); 39 Src1Name = getRegName(MI->getOperand(1).getReg()); 40 Src2Name = getRegName(MI->getOperand(2).getReg()); 46 Src2Name = getRegName(MI->getOperand(2).getReg()); 47 Src1Name = getRegName(MI->getOperand(1).getReg()); 48 DestName = getRegName(MI->getOperand(0).getReg()); 54 Src2Name = getRegName(MI->getOperand(2).getReg()); 55 Src1Name = getRegName(MI->getOperand(1).getReg()); 56 DestName = getRegName(MI->getOperand(0).getReg()); 62 Src1Name = getRegName(MI->getOperand(2).getReg()); [all...] |
H A D | X86ATTInstPrinter.cpp | 155 printRegName(O, Op.getReg()); 183 if (SegReg.getReg()) { 190 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) 197 if (IndexReg.getReg() || BaseReg.getReg()) { 199 if (BaseReg.getReg()) 202 if (IndexReg.getReg()) {
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/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonSplitTFRCondSets.cpp | 97 int DestReg = MI->getOperand(0).getReg(); 98 int SrcReg1 = MI->getOperand(2).getReg(); 99 int SrcReg2 = MI->getOperand(3).getReg(); 115 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); 119 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); 127 int DestReg = MI->getOperand(0).getReg(); 128 int SrcReg1 = MI->getOperand(2).getReg(); 135 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); 140 addReg(MI->getOperand(1).getReg()). 145 addReg(MI->getOperand(1).getReg()) [all...] |
H A D | HexagonPeephole.cpp | 141 unsigned DstReg = Dst.getReg(); 142 unsigned SrcReg = Src.getReg(); 163 unsigned DstReg = Dst.getReg(); 164 unsigned SrcReg = Src2.getReg(); 180 unsigned DstReg = Dst.getReg(); 181 unsigned SrcReg = Src1.getReg(); 192 unsigned DstReg = Dst.getReg(); 193 unsigned SrcReg = Src.getReg(); 215 unsigned DstReg = Dst.getReg(); 216 unsigned SrcReg = Src.getReg(); [all...] |
H A D | HexagonHardwareLoops.cpp | 255 unsigned getReg() const { function in class:__anon2395::CountValue 354 unsigned PhiOpReg = Phi->getOperand(i).getReg(); 362 unsigned IndReg = DI->getOperand(1).getReg(); 364 unsigned UpdReg = DI->getOperand(0).getReg(); 380 unsigned PredR = Cond[CSz-1].getReg(); 475 IVReg = IV_Phi->getOperand(i).getReg(); // Want IV reg after bump. 500 unsigned PredReg = Cond[Cond.size()-1].getReg(); 528 if (Op2.isImm() || Op1.getReg() == IVReg) 565 if (!defWithImmediate(InitialValue->getReg())) 592 unsigned R = InitialValue->getReg(); [all...] |
H A D | HexagonNewValueJump.cpp | 154 unsigned Reg = II->getOperand(i).getReg(); 239 cmpReg1 = MI->getOperand(1).getReg(); 242 cmpOp2 = MI->getOperand(2).getReg(); 427 predReg = MI->getOperand(0).getReg(); 475 MI->getOperand(0).getReg() == predReg) { 494 cmpReg1 = MI->getOperand(1).getReg(); 499 cmpOp2 = MI->getOperand(2).getReg(); 518 (MI->getOperand(0).getReg() == cmpReg1 || 520 MI->getOperand(0).getReg() == (unsigned) cmpOp2))) { 522 unsigned feederReg = MI->getOperand(0).getReg(); [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 113 printRegName(O, Dst.getReg()); 115 printRegName(O, MO1.getReg()); 118 printRegName(O, MO2.getReg()); 135 printRegName(O, Dst.getReg()); 137 printRegName(O, MO1.getReg()); 155 MI->getOperand(0).getReg() == ARM::SP && 167 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP && 172 printRegName(O, MI->getOperand(1).getReg()); 180 MI->getOperand(0).getReg() == ARM::SP && 192 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/MSP430/InstPrinter/ |
H A D | MSP430InstPrinter.cpp | 50 O << getRegisterName(Op.getReg()); 73 if (!Base.getReg()) 84 if (Base.getReg()) 85 O << '(' << getRegisterName(Base.getReg()) << ')';
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/freebsd-10.0-release/contrib/llvm/lib/Target/R600/ |
H A D | R600ExpandSpecialInstrs.cpp | 79 MI.getOperand(0).getReg(), // dst 80 MI.getOperand(1).getReg(), // src0 116 DstReg = MI.getOperand(Chan).getReg(); 121 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); 147 DstReg = MI.getOperand(Chan-2).getReg(); 150 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); 170 unsigned DstReg = MI.getOperand(0).getReg(); 221 TII->getOperandIdx(MI, R600Operands::DST)).getReg(); 223 TII->getOperandIdx(MI, R600Operands::SRC0)).getReg(); 230 Src1 = MI.getOperand(Src1Idx).getReg(); [all...] |
H A D | AMDGPUIndirectAddressing.cpp | 100 TII->getIndirectAddrStoreRegClass(MI.getOperand(0).getReg()); 102 if (MI.getOperand(1).getReg() == AMDGPU::INDIRECT_BASE_ADDR) { 114 MI.getOperand(0).getReg(), // Value 116 MI.getOperand(1).getReg()); // Offset 222 RegisterAddressMap.find(MO.getReg()) != RegisterAddressMap.end()) { 223 unsigned Reg = MO.getReg(); 250 if (MI.getOperand(1).getReg() == AMDGPU::INDIRECT_BASE_ADDR) { 262 MI.getOperand(0).getReg()) 269 MI.getOperand(0).getReg()) 302 MI.getOperand(0).getReg(), // Valu [all...] |
H A D | SILowerControlFlow.cpp | 179 unsigned Reg = MI.getOperand(0).getReg(); 180 unsigned Vcc = MI.getOperand(1).getReg(); 197 unsigned Dst = MI.getOperand(0).getReg(); 198 unsigned Src = MI.getOperand(1).getReg(); 217 unsigned Dst = MI.getOperand(0).getReg(); 218 unsigned Src = MI.getOperand(1).getReg(); 231 unsigned Dst = MI.getOperand(0).getReg(); 232 unsigned Vcc = MI.getOperand(1).getReg(); 233 unsigned Src = MI.getOperand(2).getReg(); 246 unsigned Dst = MI.getOperand(0).getReg(); [all...] |
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/AsmPrinter/ |
H A D | AsmPrinterDwarf.cpp | 180 if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) { 181 if (Src.getReg() == MachineLocation::VirtualFP) { 185 OutStreamer.EmitCFIDefCfa(RI->getDwarfRegNum(Src.getReg(), true), 188 } else if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) { 190 OutStreamer.EmitCFIDefCfaRegister(RI->getDwarfRegNum(Dst.getReg(), true)); 193 OutStreamer.EmitCFIOffset(RI->getDwarfRegNum(Src.getReg(), true),
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/freebsd-10.0-release/contrib/llvm/lib/CodeGen/ |
H A D | OptimizePHIs.cpp | 87 unsigned DstReg = MI->getOperand(0).getReg(); 99 unsigned SrcReg = MI->getOperand(i).getReg(); 108 TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg())) 109 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg()); 130 unsigned DstReg = MI->getOperand(0).getReg(); 167 unsigned OldReg = MI->getOperand(0).getReg();
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H A D | ExpandPostRAPseudos.cpp | 74 CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true)); 85 unsigned DstReg = MI->getOperand(0).getReg(); 86 unsigned InsReg = MI->getOperand(2).getReg(); 147 if (SrcMO.getReg() == DstMO.getReg()) { 165 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
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H A D | TwoAddressInstructionPass.cpp | 197 unsigned MOReg = MO.getReg(); 201 UseRegs.insert(MO.getReg()); 210 DefReg = MO.getReg(); 270 unsigned MOReg = MO.getReg(); 345 DstReg = MI.getOperand(0).getReg(); 346 SrcReg = MI.getOperand(1).getReg(); 348 DstReg = MI.getOperand(0).getReg(); 349 SrcReg = MI.getOperand(2).getReg(); 438 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) 442 DstReg = MI.getOperand(ti).getReg(); [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 143 unsigned Reg = MO.getReg(); 173 SReg = MI->getOperand(1).getReg(); 202 unsigned Reg = MO.getReg(); 225 unsigned DefReg = MODef.getReg(); 255 return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg()); 259 unsigned DPRReg = MI->getOperand(1).getReg(); 260 unsigned SPRReg = MI->getOperand(2).getReg(); 263 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg()); 264 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg()); 281 unsigned FullReg = SPRMI->getOperand(1).getReg(); [all...] |
H A D | MLxExpansionPass.cpp | 89 unsigned Reg = MI->getOperand(1).getReg(); 99 Reg = DefMI->getOperand(1).getReg(); 105 Reg = DefMI->getOperand(2).getReg(); 117 unsigned Reg = MI->getOperand(0).getReg(); 128 Reg = UseMI->getOperand(0).getReg(); 143 unsigned Reg = MI->getOperand(1).getReg(); 157 unsigned SrcReg = DefMI->getOperand(i).getReg(); 165 Reg = DefMI->getOperand(1).getReg(); 171 Reg = DefMI->getOperand(2).getReg(); 274 unsigned DstReg = MI->getOperand(0).getReg(); [all...] |
H A D | ARMAsmPrinter.cpp | 222 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm()); 232 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) 235 unsigned Reg = MLoc.getReg(); 342 unsigned Reg = MO.getReg(); 430 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg()) 446 unsigned Reg = MI->getOperand(OpNum).getReg(); 473 unsigned RegBegin = MO.getReg(); 487 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg()); 512 unsigned Reg = MO.getReg(); 521 unsigned Reg = MI->getOperand(OpNum).getReg(); [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 56 return Ctx.getRegisterInfo().getEncodingValue(MO.getReg()) & 0x7; 70 unsigned SrcReg = MI.getOperand(OpNum).getReg(); 170 if ((BaseReg.getReg() != 0 && 171 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || 172 (IndexReg.getReg() != 0 && 173 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) 185 if ((BaseReg.getReg() != 0 && 186 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || 187 (IndexReg.getReg() != 0 && 188 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64AsmPrinter.cpp | 36 return MachineLocation(MI->getOperand(0).getReg(), 50 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) { 71 if (MO.getReg() == AArch64::XSP || MO.getReg() == AArch64::WSP) { 76 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) { 171 O << AArch64InstPrinter::getRegisterName(MO.getReg()); 270 O << '[' << AArch64InstPrinter::getRegisterName(MO.getReg()) << ']'; 285 OS << '[' << AArch64InstPrinter::getRegisterName(MI->getOperand(0).getReg());
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/freebsd-10.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86CodeEmitter.cpp | 187 unsigned Reg = MO.getReg(); 489 unsigned BaseReg = Base.getReg(); 494 assert(IndexReg.getReg() == 0 && Is64BitMode && 515 IndexReg.getReg() == 0 && 553 assert(IndexReg.getReg() != X86::ESP && 554 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 587 if (IndexReg.getReg()) 588 IndexRegNo = getX86RegNum(IndexReg.getReg()); 595 if (IndexReg.getReg()) 596 IndexRegNo = getX86RegNum(IndexReg.getReg()); [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCCTRLoops.cpp | 158 unsigned getReg() const { function in class:__anon2461::CountValue 177 if (isReg()) { OS << PrintReg(getReg()); } 284 unsigned DefReg = MPhi->getOperand(0).getReg(); 290 MachineInstr *DI = MRI->getVRegDef(MPhi->getOperand(i).getReg()); 326 unsigned PredReg = LastI->getOperand(1).getReg(); 364 RI = MRI->reg_begin(IV_Opnd->getReg()), RE = MRI->reg_end(); 370 MI->getOperand(0).getReg() == PredReg) { 386 const MachineInstr *IV_DefInstr = MRI->getVRegDef(IV_Opnd->getReg()); 392 unsigned InitialValueReg = InitialValue->getReg(); 401 MRI->getVRegDef(DefInstr->getOperand(1).getReg()); [all...] |
H A D | PPCInstrInfo.cpp | 94 SrcReg = MI.getOperand(1).getReg(); 95 DstReg = MI.getOperand(0).getReg(); 118 return MI->getOperand(0).getReg(); 142 return MI->getOperand(0).getReg(); 172 unsigned Reg0 = MI->getOperand(0).getReg(); 173 unsigned Reg1 = MI->getOperand(1).getReg(); 174 unsigned Reg2 = MI->getOperand(2).getReg(); 194 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); 405 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430AsmPrinter.cpp | 70 O << MSP430InstPrinter::getRegisterName(MO.getReg()); 119 if (Disp.isImm() && !Base.getReg()) 124 if (Base.getReg()) {
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/freebsd-10.0-release/contrib/llvm/include/llvm/MC/MCParser/ |
H A D | MCParsedAsmOperand.h | 49 virtual unsigned getReg() const = 0;
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