Searched refs:TRI (Results 1 - 25 of 187) sorted by relevance

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/freebsd-10.0-release/contrib/llvm/lib/CodeGen/
H A DLiveRegMatrix.cpp50 TRI = MF.getTarget().getRegisterInfo();
55 unsigned NumRegUnits = TRI->getNumRegUnits();
73 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
74 << " to " << PrintReg(PhysReg, TRI) << ':');
78 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
79 DEBUG(dbgs() << ' ' << PrintRegUnit(*Units, TRI));
88 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
89 << " from " << PrintReg(PhysReg, TRI) << ':');
91 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
92 DEBUG(dbgs() << ' ' << PrintRegUnit(*Units, TRI));
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H A DAllocationOrder.cpp34 const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo(); local
36 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
43 dbgs() << ' ' << PrintReg(Hints[I], TRI);
H A DRegisterCoalescer.h29 const TargetRegisterInfo &TRI; member in class:llvm::CoalescerPair
63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
H A DRegisterClassInfo.cpp32 RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0)
40 if (MF->getTarget().getRegisterInfo() != TRI) {
41 TRI = MF->getTarget().getRegisterInfo();
42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
47 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
52 CSRNum.resize(TRI->getNumRegs(), 0);
54 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
98 unsigned Cost = TRI->getCostPerUse(PhysReg);
117 unsigned Cost = TRI->getCostPerUse(PhysReg);
129 if (const TargetRegisterClass *Super = TRI
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H A DTargetRegisterInfo.cpp41 else if (TRI && Reg < TRI->getNumRegs())
42 OS << '%' << TRI->getName(Reg);
46 if (TRI)
47 OS << ':' << TRI->getSubRegIndexName(SubIdx);
54 // Generic printout when TRI is missing.
55 if (!TRI) {
61 if (Unit >= TRI->getNumRegUnits()) {
67 MCRegUnitRootIterator Roots(Unit, TRI);
69 OS << TRI
151 firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI) argument
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H A DRegAllocBase.h61 const TargetRegisterInfo *TRI; member in class:llvm::RegAllocBase
68 RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0), Matrix(0) {}
H A DMachineRegisterInfo.cpp22 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) argument
23 : TRI(&TRI), IsSSA(true), TracksLiveness(true) {
26 UsedRegUnits.resize(TRI.getNumRegUnits());
27 UsedPhysRegMask.resize(TRI.getNumRegs());
30 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
31 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
53 const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC);
66 const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
76 I->getRegClassConstraint(I.getOperandNo(), TII, TRI);
356 EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII) argument
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H A DMachineCopyPropagation.cpp35 const TargetRegisterInfo *TRI; member in class:__anon2170::MachineCopyPropagation
68 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
77 for (MCSubRegIterator SR(MappedDef, TRI); SR.isValid(); ++SR)
114 const TargetRegisterInfo *TRI) {
118 if (TRI->isSubRegister(SrcSrc, Def)) {
120 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def);
123 return SubIdx == TRI->getSubRegIndex(SrcDef, Src);
164 isNopCopy(CopyMI, Def, Src, TRI)) {
182 I->clearRegisterKills(Def, TRI);
192 for (MCRegAliasIterator AI(Src, TRI, tru
113 isNopCopy(MachineInstr *CopyMI, unsigned Def, unsigned Src, const TargetRegisterInfo *TRI) argument
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H A DInterferenceCache.h25 const TargetRegisterInfo *TRI; member in class:llvm::InterferenceCache
112 void revalidate(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
115 bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
120 const TargetRegisterInfo *TRI,
150 InterferenceCache() : TRI(0), LIUArray(0), MF(0), RoundRobin(0) {}
H A DRegisterScavenging.cpp36 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
41 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
75 TRI = TM.getRegisterInfo();
78 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
88 NumPhysRegs = TRI->getNumRegs();
95 const uint16_t *CSRegs = TRI->getCalleeSavedRegs(&MF);
109 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
221 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
238 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
263 DEBUG(dbgs() << "Scavenger found unused reg: " << TRI
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H A DAggressiveAntiDepBreaker.cpp122 TRI(MF.getTarget().getRegisterInfo()),
128 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]);
138 dbgs() << " " << TRI->getName(r));
148 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
159 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
172 for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
175 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
203 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
212 dbgs() << " " << TRI->getName(Reg) << "=g" <<
251 for (MCSubRegIterator SubRegs(Reg, TRI); SubReg
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/freebsd-10.0-release/contrib/llvm/lib/Target/R600/
H A DR600ExpandSpecialInstrs.cpp60 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local
166 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local
174 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg);
234 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
235 Src0 = TRI.getSubReg(Src0, SubRegIndex);
236 Src1 = TRI.getSubReg(Src1, SubRegIndex);
239 unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]);
240 unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]);
241 Src1 = TRI
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/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/
H A DMipsInstrInfo.h93 const TargetRegisterInfo *TRI) const {
94 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
101 const TargetRegisterInfo *TRI) const {
102 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
109 const TargetRegisterInfo *TRI,
116 const TargetRegisterInfo *TRI,
H A DMips16FrameLowering.h37 const TargetRegisterInfo *TRI) const;
42 const TargetRegisterInfo *TRI) const;
H A DMipsFrameLowering.cpp104 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); local
113 for (const uint16_t *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) {
114 unsigned Size = TRI.getMinimalPhysRegClass(*R)->getSize();
/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp44 const TargetRegisterInfo *TRI,
50 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) {
62 const TargetRegisterInfo *TRI,
76 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) {
157 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); local
170 if (printModifiedFPRAsmOperand(MO, TRI, AArch64::VPR128RegClass, O))
202 return printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI,
207 return printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI,
225 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI,
229 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI,
43 printModifiedFPRAsmOperand(const MachineOperand &MO, const TargetRegisterInfo *TRI, const TargetRegisterClass &RegClass, raw_ostream &O) argument
61 printModifiedGPRAsmOperand(const MachineOperand &MO, const TargetRegisterInfo *TRI, const TargetRegisterClass &RegClass, raw_ostream &O) argument
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H A DAArch64FrameLowering.h68 const TargetRegisterInfo *TRI) const;
72 const TargetRegisterInfo *TRI) const;
92 const TargetRegisterInfo *TRI,
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.h32 const ARMBaseRegisterInfo &TRI; member in class:llvm::ARMHazardRecognizer
45 TRI(tri), STI(sti), LastMI(0) {}
H A DThumb1FrameLowering.h41 const TargetRegisterInfo *TRI) const;
45 const TargetRegisterInfo *TRI) const;
H A DThumb1InstrInfo.h50 const TargetRegisterInfo *TRI) const;
56 const TargetRegisterInfo *TRI) const;
H A DThumb2InstrInfo.h52 const TargetRegisterInfo *TRI) const;
58 const TargetRegisterInfo *TRI) const;
/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.h37 const TargetRegisterInfo *TRI) const;
47 const TargetRegisterInfo *TRI) const;
H A DHexagonFrameLowering.cpp214 unsigned uniqueSuperReg(unsigned Reg, const TargetRegisterInfo *TRI) { argument
215 MCSuperRegIterator SRI(Reg, TRI);
228 const TargetRegisterInfo *TRI) const {
249 unsigned SuperReg = uniqueSuperReg(Reg, TRI);
254 unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI);
255 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg);
262 CSI[i+1].getFrameIdx(), SuperRegClass, TRI);
268 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
270 TRI);
282 const TargetRegisterInfo *TRI) cons
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/freebsd-10.0-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.h45 const TargetRegisterInfo *TRI) const;
49 const TargetRegisterInfo *TRI) const;
/freebsd-10.0-release/contrib/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.h36 const TargetRegisterInfo *TRI) const;
40 const TargetRegisterInfo *TRI) const;

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