Searched refs:TRC (Results 1 - 8 of 8) sorted by relevance

/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp80 const TargetRegisterClass *TRC);
104 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
140 const TargetRegisterClass *TRC) {
146 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
148 return TRC->contains(Reg);
282 const TargetRegisterClass *TRC = local
284 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
454 const TargetRegisterClass *TRC) {
455 unsigned Out = MRI->createVirtualRegister(TRC);
139 usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC) argument
450 createExtractSubreg(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned DReg, unsigned Lane, const TargetRegisterClass *TRC) argument
H A DARMISelLowering.cpp5979 const TargetRegisterClass *TRC = isThumb2 ? local
5982 unsigned scratch = MRI.createVirtualRegister(TRC);
5983 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
6090 const TargetRegisterClass *TRC = isThumb2 ? local
6093 unsigned scratch = MRI.createVirtualRegister(TRC);
6094 unsigned scratch2 = MRI.createVirtualRegister(TRC);
6198 const TargetRegisterClass *TRC = isThumb2 ? local
6201 unsigned storesuccess = MRI.createVirtualRegister(TRC);
6255 unsigned tmpRegLo = MRI.createVirtualRegister(TRC);
6259 unsigned tmpRegHi = MRI.createVirtualRegister(TRC);
6345 const TargetRegisterClass *TRC = isThumb ? local
6451 const TargetRegisterClass *TRC = Subtarget->isThumb() ? local
6875 const TargetRegisterClass *TRC = isThumb2 ? local
[all...]
H A DARMLoadStoreOptimizer.cpp1753 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); local
1754 MRI->constrainRegClass(EvenReg, TRC);
1755 MRI->constrainRegClass(OddReg, TRC);
/freebsd-10.0-release/usr.sbin/lpr/lpd/
H A Dprintjob.c1500 #define TRC(q) (((q)-' ')&0177) macro
1514 d = dropit(c = TRC(cc = *sp++));
1539 case TRC('_'):
1540 case TRC(';'):
1541 case TRC(','):
1542 case TRC('g'):
1543 case TRC('j'):
1544 case TRC('p'):
1545 case TRC('q'):
1546 case TRC('
[all...]
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp476 const TargetRegisterClass *TRC =
485 TRC == MRI->getRegClass(SrcReg)) {
491 VRBase = MRI->createVirtualRegister(TRC);
505 VRBase = MRI->createVirtualRegister(TRC);
610 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
612 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
/freebsd-10.0-release/contrib/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp2522 const TargetRegisterClass *TRC; local
2524 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2525 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2528 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2557 const TargetRegisterClass *TRC; local
2559 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2560 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2561 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2564 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp574 const TargetRegisterClass *TRC; local
576 TRC = &Hexagon::PredRegsRegClass;
578 TRC = &Hexagon::IntRegsRegClass;
580 TRC = &Hexagon::DoubleRegsRegClass;
585 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp335 const TargetRegisterClass *TRC local
337 unsigned scratch = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
407 const TargetRegisterClass *TRC, *TRCsp; local
409 TRC = &AArch64::GPR64RegClass;
412 TRC = &AArch64::GPR32RegClass;
430 unsigned scratch = MRI.createVirtualRegister(TRC);

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