Searched refs:ProcIndices (Results 1 - 3 of 3) sorted by relevance
/freebsd-10.0-release/contrib/llvm/utils/TableGen/ |
H A D | CodeGenSchedule.cpp | 508 SchedClasses.back().ProcIndices.push_back(0); 520 IdxVec ProcIndices(1, 0); 522 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices); 548 if (SC.ProcIndices[0] != 0) 552 IdxVec ProcIndices; 554 ProcIndices.push_back(0); 559 ProcIndices.push_back(0); 572 ProcIndices.push_back(ProcModel.Index); 586 if (!std::count(ProcIndices.begin(), ProcIndices [all...] |
H A D | CodeGenSchedule.h | 99 IdxVec ProcIndices; member in struct:llvm::CodeGenSchedTransition 109 /// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor. 113 /// subtargets. ProcIndices contains 0 for any processor. 117 /// instructions to this class. ProcIndices contains all the processors that 122 /// resolved at runtime. ProcIndices contains the set of processors that may 123 /// require the class. ProcIndices are propagated through SchedClasses as 135 IdxVec ProcIndices; member in struct:llvm::CodeGenSchedClass 342 const IdxVec &OperReads, const IdxVec &ProcIndices); 379 unsigned FromClassIdx, const IdxVec &ProcIndices); 391 const IdxVec &ProcIndices); [all...] |
H A D | SubtargetEmitter.cpp | 862 if (TI->ProcIndices[0] == 0) { 866 IdxIter PIPos = std::find(TI->ProcIndices.begin(), 867 TI->ProcIndices.end(), ProcModel.Index); 868 if (PIPos != TI->ProcIndices.end()) { 880 // If ProcIndices contains 0, this class applies to all processors. 881 assert(!SCI->ProcIndices.empty() && "expect at least one procidx"); 882 if (SCI->ProcIndices[0] != 0) { 883 IdxIter PIPos = std::find(SCI->ProcIndices.begin(), 884 SCI->ProcIndices.end(), ProcModel.Index); 885 if (PIPos == SCI->ProcIndices 1323 IdxVec ProcIndices; local [all...] |
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