Searched refs:PhysReg (Results 1 - 22 of 22) sorted by relevance

/freebsd-10.0-release/contrib/llvm/lib/CodeGen/
H A DLiveRegMatrix.cpp72 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { argument
74 << " to " << PrintReg(PhysReg, TRI) << ':');
76 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
77 MRI->setPhysRegUsed(PhysReg);
78 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
87 unsigned PhysReg = VRM->getPhys(VirtReg.reg); local
89 << " from " << PrintReg(PhysReg, TRI) << ':');
91 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
100 unsigned PhysReg) {
111 // The BitVector is indexed by PhysReg, no
99 checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg) argument
117 checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg) argument
136 checkInterference(LiveInterval &VirtReg, unsigned PhysReg) argument
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H A DRegAllocFast.cpp73 unsigned PhysReg; // Currently held here. member in struct:__anon2197::RAFast::LiveReg
78 : LastUse(0), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false) {}
124 void markRegUsedInInstr(unsigned PhysReg) { argument
125 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
130 bool isRegUsedInInstr(unsigned PhysReg) const {
131 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
177 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
178 unsigned calcSpillCost(unsigned PhysReg) const;
179 void assignVirtToPhysReg(LiveReg&, unsigned PhysReg);
186 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg);
348 unsigned PhysReg = MO.getReg(); local
402 definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState) argument
493 assignVirtToPhysReg(LiveReg &LR, unsigned PhysReg) argument
502 assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) argument
542 unsigned PhysReg = *I; local
666 setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) argument
740 unsigned PhysReg = LRI->PhysReg; local
763 unsigned PhysReg = LRI->PhysReg; local
972 unsigned PhysReg = LRI->PhysReg; local
1028 unsigned PhysReg = LRI->PhysReg; local
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H A DInterferenceCache.h39 /// of PhysReg in all basic blocks.
41 /// PhysReg - The register currently represented.
42 unsigned PhysReg; member in class:llvm::InterferenceCache::Entry
63 /// RegUnitInfo - Information tracked about each RegUnit in PhysReg.
85 /// Info for each RegUnit in PhysReg. It is very rare ofr a PHysReg to have
96 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0), LIS(0) {}
100 PhysReg = 0;
106 unsigned getPhysReg() const { return PhysReg; }
146 // get - Get a valid entry for PhysReg.
147 Entry *get(unsigned PhysReg);
192 setPhysReg(InterferenceCache &Cache, unsigned PhysReg) argument
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H A DRegisterClassInfo.cpp94 unsigned PhysReg = RawOrder[i]; local
96 if (Reserved.test(PhysReg))
98 unsigned Cost = TRI->getCostPerUse(PhysReg);
101 if (CSRNum[PhysReg])
102 // PhysReg aliases a CSR, save it for later.
103 CSRAlias.push_back(PhysReg);
107 RCI.Order[N++] = PhysReg;
116 unsigned PhysReg = CSRAlias[i]; local
117 unsigned Cost = TRI->getCostPerUse(PhysReg);
120 RCI.Order[N++] = PhysReg;
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H A DAllocationOrder.h77 /// Return true if PhysReg is a preferred register.
78 bool isHint(unsigned PhysReg) const {
79 return std::find(Hints.begin(), Hints.end(), PhysReg) != Hints.end();
H A DRegisterCoalescer.h68 CoalescerPair(unsigned VirtReg, unsigned PhysReg, argument
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
H A DVirtRegMap.cpp246 // assigned PhysReg must be marked as live-in to those blocks.
247 unsigned PhysReg = VRM->getPhys(VirtReg); local
248 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
256 if (!LiveIn[i]->isLiveIn(PhysReg))
257 LiveIn[i]->addLiveIn(PhysReg);
287 unsigned PhysReg = VRM->getPhys(VirtReg); local
288 assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
290 assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
298 SuperKills.push_back(PhysReg);
309 SuperDeads.push_back(PhysReg);
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H A DInterferenceCache.cpp38 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) { argument
39 unsigned E = PhysRegEntries[PhysReg];
40 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) {
56 Entries[E].reset(PhysReg, LIUArray, TRI, MF);
57 PhysRegEntries[PhysReg] = E;
71 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i)
82 PhysReg = physReg;
88 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
97 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) {
168 if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) {
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H A DRegAllocBasic.cpp112 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
164 // Spill or split all live virtual registers currently unified under PhysReg
167 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, argument
174 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
186 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
190 // Spill each interfering vreg allocated to PhysReg or an alias.
228 while (unsigned PhysReg = Order.next()) {
229 // Check for interference in PhysReg
230 switch (Matrix->checkInterference(VirtReg, PhysReg)) {
232 // PhysReg i
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H A DRegAllocGreedy.cpp181 unsigned PhysReg; member in struct:__anon2201::RAGreedy::GlobalSplitCandidate
186 // Interference for PhysReg.
194 PhysReg = Reg;
214 /// Candidate info for for each PhysReg in AllocationOrder.
440 unsigned PhysReg; local
441 while ((PhysReg = Order.next()))
442 if (!Matrix->checkInterference(VirtReg, PhysReg))
444 if (!PhysReg || Order.isHint())
445 return PhysReg;
447 // PhysReg i
513 canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, bool IsHint, EvictionCost &MaxCost) argument
584 evictInterference(LiveInterval &VirtReg, unsigned PhysReg, SmallVectorImpl<LiveInterval*> &NewVRegs) argument
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H A DLiveRangeCalc.h113 /// PhysReg, when set, is used to verify live-in lists on basic blocks.
117 unsigned PhysReg);
167 /// PhysReg, when set, is used to verify live-in lists on basic blocks.
168 void extend(LiveInterval *LI, SlotIndex Kill, unsigned PhysReg = 0);
H A DLiveRangeCalc.cpp137 unsigned PhysReg) {
154 if (findReachingDefs(LI, KillMBB, Kill, PhysReg))
176 unsigned PhysReg) {
196 if (TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
197 !MBB->isLiveIn(PhysReg)) {
135 extend(LiveInterval *LI, SlotIndex Kill, unsigned PhysReg) argument
173 findReachingDefs(LiveInterval *LI, MachineBasicBlock *KillMBB, SlotIndex Kill, unsigned PhysReg) argument
H A DMachineRegisterInfo.cpp398 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, argument
400 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
404 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
H A DMachineBasicBlock.cpp346 MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) { argument
348 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg");
353 bool LiveIn = isLiveIn(PhysReg);
361 if (I->getOperand(1).getReg() == PhysReg) {
371 .addReg(PhysReg, RegState::Kill);
373 addLiveIn(PhysReg);
/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/
H A DLiveRegMatrix.h87 /// assigned to PhysReg or its aliases. This interference could be resolved
97 /// regmask operand that doesn't preserve PhysReg. This typically means
98 /// VirtReg is live across a call, and PhysReg isn't call-preserved.
102 /// Check for interference before assigning VirtReg to PhysReg.
103 /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg).
106 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
108 /// Assign VirtReg to PhysReg.
110 /// update VirtRegMap. The live range is expected to be available in PhysReg.
111 void assign(LiveInterval &VirtReg, unsigned PhysReg);
113 /// Unassign VirtReg from its PhysReg
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H A DRegisterClassInfo.h107 /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR.
108 unsigned getLastCalleeSavedAlias(unsigned PhysReg) const {
109 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
110 if (unsigned N = CSRNum[PhysReg])
H A DMachineRegisterInfo.h292 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
295 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
436 /// canReserveReg - Returns true if PhysReg can be used as a reserved
439 bool canReserveReg(unsigned PhysReg) const {
440 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
453 /// isReserved - Returns true when PhysReg is a reserved register.
458 bool isReserved(unsigned PhysReg) const {
459 return getReservedRegs().test(PhysReg);
462 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
468 bool isAllocatable(unsigned PhysReg) cons
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H A DMachineOperand.h457 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
461 static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) { argument
463 assert(PhysReg < (1u << 30) && "Not a physical register");
464 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
467 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
468 bool clobbersPhysReg(unsigned PhysReg) const {
469 return clobbersPhysReg(getRegMask(), PhysReg);
H A DMachineBasicBlock.h299 /// Add PhysReg as live in to this block, and ensure that there is a copy of
300 /// PhysReg to a virtual register of class RC. Return the virtual register
301 /// that is a copy of the live in PhysReg.
302 unsigned addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC);
/freebsd-10.0-release/contrib/llvm/utils/TableGen/
H A DFastISelEmitter.cpp404 std::string PhysReg;
407 return PhysReg;
411 return PhysReg;
413 PhysReg += cast<StringInit>(OpLeafRec->getValue("Namespace")->getValue())
415 PhysReg += "::";
416 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName();
417 return PhysReg;
519 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target);
520 if (PhysReg.empty()) {
530 PhysRegInputs->push_back(PhysReg);
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/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.cpp113 unsigned &PhysReg, int &Cost) {
126 PhysReg = Reg;
468 unsigned PhysReg = 0;
471 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
472 assert((PhysReg == 0 || !isChain) &&
480 PhysReg = 0;
489 : SDep(OpSU, SDep::Data, PhysReg);
110 CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) argument
H A DSelectionDAGBuilder.cpp5745 std::pair<unsigned, const TargetRegisterClass*> PhysReg = local
5755 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5759 MVT RegVT = *PhysReg.second->vt_begin();
5784 if (unsigned AssignedReg = PhysReg.first) {
5785 const TargetRegisterClass *RC = PhysReg.second;
5817 if (const TargetRegisterClass *RC = PhysReg.second) {

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