/freebsd-10.0-release/contrib/llvm/utils/TableGen/ |
H A D | AsmWriterInst.h | 87 std::vector<AsmWriterOperand> Operands; member in class:llvm::AsmWriterInst 104 if (!Operands.empty() && 105 Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand) 106 Operands.back().Str.append(Str); 108 Operands.push_back(AsmWriterOperand(Str));
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H A D | FastISelEmitter.cpp | 116 SmallVector<OpKind, 3> Operands; 119 return Operands < O.Operands; 122 return Operands == O.Operands; 125 bool empty() const { return Operands.empty(); } 128 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 129 if (Operands[i].isImm() && Operands[i].getImmCode() != 0) 138 for (unsigned i = 0, e = Operands [all...] |
H A D | AsmWriterInst.cpp | 87 Operands.push_back( 119 Operands.push_back( 196 Operands.push_back(AsmWriterOperand("PrintSpecial", 202 unsigned OpNo = CGI.Operands.getOperandNamed(VarName); 203 CGIOperandList::OperandInfo OpInfo = CGI.Operands[OpNo]; 206 Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName, 213 Operands.push_back(AsmWriterOperand("return;", 222 if (Operands.size() != Other.Operands.size()) return ~1; 225 for (unsigned i = 0, e = Operands [all...] |
H A D | PseudoLoweringEmitter.cpp | 92 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) 96 Insn.Operands[BaseIdx + i].Rec->getName() + "'"); 100 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) 102 OpsAdded += Insn.Operands[i].MINumOperands; 145 if (Insn.Operands.size() != Dag->getNumArgs()) 150 for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) 151 NumMIOperands += Insn.Operands[i].MINumOperands; 159 // Operands that are a sublass of OperandWithDefaultOp have default values. 170 for (unsigned i = 0, e = SourceInsn.Operands.size(); i != e; ++i) 171 SourceOperands[SourceInsn.Operands[ [all...] |
H A D | InstrInfoEmitter.cpp | 76 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) { 85 DagInit *MIOI = Inst.Operands[i].MIOperandInfo; 89 OperandList.push_back(Inst.Operands[i]); 91 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) { 92 OperandList.push_back(Inst.Operands[i]); 122 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand")) 127 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand")) 132 assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type."); 133 Res += Inst.Operands[i].OperandType; 139 Inst.Operands[ [all...] |
H A D | AsmWriterEmitter.cpp | 108 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) { 111 O << " " << FirstInst.Operands[i].getCode(); 119 FirstInst.Operands[i])); 125 AWI.Operands[i])); 155 if (Inst->Operands.empty()) 158 Command = " " + Inst->Operands[0].getCode() + "\n"; 197 if (!FirstInst || FirstInst->Operands.size() == Op) 205 size_t MaxSize = FirstInst->Operands.size(); 216 OtherInst->Operands.size() > FirstInst->Operands [all...] |
H A D | CodeEmitterGen.cpp | 131 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { 133 OpIdx = CGI.Operands[OpIdx].MIOperandNo; 134 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && 137 unsigned NumberOps = CGI.Operands.size(); 141 CGI.Operands.isFlatOperandNotEmitted(NumberedOp)) 147 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx); 148 std::string &EncoderMethodName = CGI.Operands[SO.first].EncoderMethodName;
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H A D | CodeGenInstruction.cpp | 292 : TheDef(R), Operands(R), InferredFrom(0) { 306 isPredicable = Operands.isPredicable || R->getValueAsBit("isPredicable"); 335 ParseConstraints(R->getValueAsString("Constraints"), Operands); 338 Operands.ProcessDisableEncoding(R->getValueAsString("DisableEncoding")); 501 // If both are Operands with the same MVT, allow the conversion. It's 549 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) { 554 if (ResultInst->Operands[i].MINumOperands == 1 && 555 ResultInst->Operands[i].getTiedRegister() != -1) 561 Record *InstOpRec = ResultInst->Operands[i].Rec; 562 unsigned NumSubOps = ResultInst->Operands[ [all...] |
/freebsd-10.0-release/contrib/llvm/include/llvm/MC/ |
H A D | MCInst.h | 153 SmallVector<MCOperand, 8> Operands; member in class:llvm::MCInst 163 const MCOperand &getOperand(unsigned i) const { return Operands[i]; } 164 MCOperand &getOperand(unsigned i) { return Operands[i]; } 165 unsigned getNumOperands() const { return Operands.size(); } 168 Operands.push_back(Op); 171 void clear() { Operands.clear(); } 172 size_t size() { return Operands.size(); } 175 iterator begin() { return Operands.begin(); } 176 iterator end() { return Operands.end(); } 178 return Operands [all...] |
H A D | MCTargetAsmParser.h | 125 /// \param Operands [out] - The list of parsed operands, this returns 130 SmallVectorImpl<MCParsedAsmOperand*> &Operands) = 0; 156 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 176 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) = 0;
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/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 69 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 76 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 84 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 92 ParseNEONLane(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 96 ParseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 100 ParseImmWithLSLOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands); 103 ParseCondCodeOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands); 106 ParseCRxOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands); 109 ParseFPImmOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands); 112 ParseNamedImmOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { argument 1073 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Mnemonic) argument 1182 ParseNEONLane(SmallVectorImpl<MCParsedAsmOperand*> &Operands, uint32_t NumLanes) argument 1286 ParseImmWithLSLOperand( SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 1338 ParseCondCodeOperand( SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 1358 ParseCRxOperand( SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 1390 ParseFPImmOperand( SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 1483 ParseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands, uint32_t &NumLanes) argument 1540 ParseNamedImmOperand(const NamedImmMapper &Mapper, SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 1587 ParseSysRegOperand( SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 1607 ParseLSXAddressOperand( SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 1657 ParseShiftExtend( SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 1729 validateInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 1817 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 1956 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCStreamer &Out, unsigned &ErrorInfo, bool MatchingInlineAsm) argument [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/SystemZ/AsmParser/ |
H A D | SystemZAsmParser.cpp | 313 parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 319 parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 323 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 341 SmallVectorImpl<MCParsedAsmOperand*> &Operands) 345 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 351 parseGR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { argument 352 return parseRegister(Operands, 'r', GR32Regs, SystemZOperand::GR32Reg); 355 parseGR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { argument 356 return parseRegister(Operands, 'r', GR64Regs, SystemZOperand::GR64Reg); 359 parseGR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { argument 363 parseADDR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 368 parseADDR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 373 parseADDR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 377 parseFP32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 381 parseFP64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 385 parseFP128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 389 parseBDAddr32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 393 parseBDAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 397 parseBDXAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 469 parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands, char Prefix, const unsigned *Regs, SystemZOperand::RegisterKind Kind, bool IsAddress) argument 486 parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands, const unsigned *Regs, SystemZOperand::RegisterKind RegKind, bool HasIndex) argument 560 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 593 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Mnemonic) argument 620 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCStreamer &Out, unsigned &ErrorInfo, bool MatchingInlineAsm) argument 673 parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 70 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 78 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 81 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 86 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands); 89 parseCPURegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands); 92 parseCPU64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands); 95 parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands); 98 parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands); 101 parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands); 103 bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 701 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCStreamer &Out, unsigned &ErrorInfo, bool MatchingInlineAsm) argument 906 tryParseRegisterOperand( SmallVectorImpl<MCParsedAsmOperand*> &Operands, bool is64BitReg) argument 1255 parseCPU64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 1278 searchSymbolAlias( SmallVectorImpl<MCParsedAsmOperand*> &Operands, unsigned RegisterKind) argument 1317 parseCPURegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 1339 parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 1369 parseHW64Regs( SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 1399 parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 1479 parseMathOperation(StringRef Name, SMLoc NameLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 1531 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument [all...] |
/freebsd-10.0-release/contrib/llvm/include/llvm/Analysis/ |
H A D | ScalarEvolutionExpressions.h | 139 const SCEV *const *Operands; member in class:llvm::SCEVNAryExpr 144 : SCEV(ID, T), Operands(O), NumOperands(N) {} 150 return Operands[i]; 154 op_iterator op_begin() const { return Operands; } 155 op_iterator op_end() const { return Operands + NumOperands; } 293 const SCEV *getStart() const { return Operands[0]; } 581 SmallVector<const SCEV *, 2> Operands; local 583 Operands.push_back(visit(Expr->getOperand(i))); 584 return SE.getAddExpr(Operands); 588 SmallVector<const SCEV *, 2> Operands; local 599 SmallVector<const SCEV *, 2> Operands; local 607 SmallVector<const SCEV *, 2> Operands; local 614 SmallVector<const SCEV *, 2> Operands; local 672 SmallVector<const SCEV *, 2> Operands; local [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Analysis/ |
H A D | ScalarEvolutionNormalization.cpp | 109 SmallVector<const SCEV *, 8> Operands; local 116 Operands.push_back(TransformSubExpr(*I, LUser, 0)); 119 const SCEV *Result = SE.getAddRecExpr(Operands, L, SCEV::FlagAnyWrap); 160 SmallVector<const SCEV *, 8> Operands; local 168 Operands.push_back(N); 173 case scAddExpr: return SE.getAddExpr(Operands); 174 case scMulExpr: return SE.getMulExpr(Operands); 175 case scSMaxExpr: return SE.getSMaxExpr(Operands); 176 case scUMaxExpr: return SE.getUMaxExpr(Operands);
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/freebsd-10.0-release/contrib/llvm/lib/Target/MBlaze/AsmParser/ |
H A D | MBlazeAsmParser.cpp | 37 MBlazeOperand *ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands); 42 MBlazeOperand* ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands); 49 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 67 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 325 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 329 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, 342 if (ErrorInfo >= Operands.size()) 345 ErrorLoc = ((MBlazeOperand*)Operands[ErrorInfo])->getStartLoc(); 357 ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { argument 358 if (Operands 324 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCStreamer &Out, unsigned &ErrorInfo, bool MatchingInlineAsm) argument 468 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 495 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument [all...] |
/freebsd-10.0-release/sys/contrib/dev/acpica/components/executer/ |
H A D | excreate.c | 84 AliasNode = (ACPI_NAMESPACE_NODE *) WalkState->Operands[0]; 85 TargetNode = (ACPI_NAMESPACE_NODE *) WalkState->Operands[1]; 205 Status = AcpiNsAttachObject ((ACPI_NAMESPACE_NODE *) WalkState->Operands[0], 262 ObjDesc->Mutex.SyncLevel = (UINT8) WalkState->Operands[1]->Integer.Value; 263 ObjDesc->Mutex.Node = (ACPI_NAMESPACE_NODE *) WalkState->Operands[0]; 403 ACPI_OPERAND_OBJECT **Operand = &WalkState->Operands[0]; 455 ACPI_OPERAND_OBJECT **Operand = &WalkState->Operands[0]; 509 ACPI_OPERAND_OBJECT **Operand = &WalkState->Operands[0];
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/freebsd-10.0-release/sys/contrib/dev/acpica/components/dispatcher/ |
H A D | dsopcode.c | 379 WalkState->Operands[0], WalkState->Operands[1], 380 WalkState->Operands[2], WalkState->Operands[3]); 387 WalkState->Operands[0], WalkState->Operands[1], 388 NULL, WalkState->Operands[2]); 465 OperandDesc = WalkState->Operands[WalkState->NumOperands - 1]; 474 OperandDesc = WalkState->Operands[WalkState->NumOperands - 2]; 556 Operand = &WalkState->Operands[ [all...] |
H A D | dscontrol.c | 281 Status = AcpiExResolveToValue (&WalkState->Operands [0], WalkState); 292 WalkState->ReturnDesc = WalkState->Operands[0]; 329 AcpiUtRemoveReference (WalkState->Operands [0]); 332 WalkState->Operands [0] = NULL;
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H A D | dswexec.c | 127 Status = AcpiExResolveToValue (&WalkState->Operands [0], WalkState); 133 ObjDesc = WalkState->Operands [0]; 461 &(WalkState->Operands [WalkState->NumOperands -1]), 482 (WalkState->Operands[0]->Common.Type == ACPI_TYPE_LOCAL_REFERENCE) && 483 (WalkState->Operands[1]->Common.Type == ACPI_TYPE_LOCAL_REFERENCE) && 484 (WalkState->Operands[0]->Reference.Class == 485 WalkState->Operands[1]->Reference.Class) && 486 (WalkState->Operands[0]->Reference.Value == 487 WalkState->Operands[1]->Reference.Value)) 620 WalkState->Operands[ [all...] |
H A D | dswload2.c | 433 WalkState->Operands[0] = (void *) Node; 580 AcpiUtRemoveReference (WalkState->Operands[i]); 581 WalkState->Operands[i] = NULL; 674 WalkState->Operands[0] = ACPI_CAST_PTR (void, Op->Named.Node); 683 WalkState->Operands[0] = NULL; 754 WalkState->Operands[0] = NULL;
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/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 231 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 269 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 276 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 2559 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2582 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 2642 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 2646 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 2660 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { argument 2666 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(), 2671 Operands 2558 tryParseShiftRegister( SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 2746 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 2783 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 2802 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 2820 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 2898 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3075 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3326 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3388 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3422 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3550 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, int Low, int High) argument 3598 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3627 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3697 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3743 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3811 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3860 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3933 cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3950 cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3967 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3982 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3995 cvtLdWriteBackRegAddrMode2(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4010 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4026 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4039 cvtStWriteBackRegAddrMode2(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4052 cvtStWriteBackRegAddrMode3(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4065 cvtLdExtTWriteBackImm(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4083 cvtLdExtTWriteBackReg(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4101 cvtStExtTWriteBackImm(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4119 cvtStExtTWriteBackReg(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4137 cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4154 cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4171 cvtLdWriteBackRegAddrMode3(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4184 cvtThumbMultiply(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4201 cvtVLDwbFixed(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4214 cvtVLDwbRegister(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4229 cvtVSTwbFixed(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4242 cvtVSTwbRegister(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4259 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4508 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4583 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Mnemonic) argument 4880 shouldOmitCCOutOperand(StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 5028 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 5298 validateInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 5731 processInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 7546 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCStreamer &Out, unsigned &ErrorInfo, bool MatchingInlineAsm) argument [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Transforms/Vectorize/ |
H A D | VecUtils.cpp | 118 ArrayRef<Value *> Operands = Chain.slice(i, VF); local 120 int Cost = getTreeCost(Operands); 124 vectorizeTree(Operands, VF); 160 ValueList Operands; local 165 Operands.push_back(I); 170 bool Vectorized = vectorizeStoreChain(Operands, costThreshold); 174 VectorizedStores.insert(Operands.begin(), Operands.end()); 226 void BoUpSLP::vectorizeArith(ArrayRef<Value *> Operands) { argument 227 Value *Vec = vectorizeTree(Operands, Operand 362 ValueList Operands; local 372 ValueList Operands; local 473 ValueList Operands; local 516 ValueList Operands; local 552 ValueList Operands; local [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 521 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 565 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 1830 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1898 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc)); 1901 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc)); 1920 Operands.push_back(X86Operand::CreateToken("*", Loc)); 1926 Operands.push_back(Op); 1937 Operands.push_back(Op); 1957 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc)); 1963 Operands 1829 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 2200 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCStreamer &Out, unsigned &ErrorInfo, bool MatchingInlineAsm) argument [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/AsmParser/ |
H A D | PPCAsmParser.cpp | 129 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands); 135 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 163 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 421 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 474 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 479 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { 483 ProcessInstruction(Inst, Operands); 494 if (ErrorInfo >= Operands.size()) 497 ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc(); 560 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { argument 420 ProcessInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 473 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCStreamer &Out, unsigned &ErrorInfo, bool MatchingInlineAsm) argument 644 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument [all...] |