Searched refs:MinLatency (Results 1 - 7 of 7) sorted by relevance
/freebsd-10.0-release/contrib/llvm/include/llvm/MC/ |
H A D | MCSchedule.h | 137 // MinLatency is the minimum latency between a register write 142 // hazard. MinLatency can always be overridden by the number of 146 // Use InstrItinerary OperandCycles as MinLatency. 157 int MinLatency; member in class:llvm::MCSchedModel 162 // If MinLatency >= 0, this may be overriden for individual load opcodes by 171 // If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles. 206 MinLatency(DefaultMinLatency), 223 IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl),
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H A D | MCInstrItineraries.h | 160 /// InstrStages override the itinerary's MinLatency property. In fact, if the 161 /// stage latencies, which may be zero, are less than MinLatency, 162 /// getStageLatency returns a value less than MinLatency. 164 /// If no stages exist, MinLatency is used. If MinLatency is invalid (<0), 170 return SchedModel->MinLatency < 0 ? 1 : SchedModel->MinLatency;
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/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonMachineScheduler.cpp | 226 unsigned MinLatency = I->getMinLatency(); local 228 Top.MaxMinLatency = std::max(MinLatency, Top.MaxMinLatency); 230 if (SU->TopReadyCycle < PredReadyCycle + MinLatency) 231 SU->TopReadyCycle = PredReadyCycle + MinLatency; 245 unsigned MinLatency = I->getMinLatency(); local 247 Bot.MaxMinLatency = std::max(MinLatency, Bot.MaxMinLatency); 249 if (SU->BotReadyCycle < SuccReadyCycle + MinLatency) 250 SU->BotReadyCycle = SuccReadyCycle + MinLatency;
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/freebsd-10.0-release/contrib/llvm/lib/CodeGen/ |
H A D | TargetSchedule.cpp | 109 // If MinLatency is invalid, then use the itinerary for MinLatency. If no 111 if (SchedModel.MinLatency < 0 && !hasInstrItineraries()) { 114 return SchedModel.MinLatency; 277 // MinLatency == -1 is for in-order processors that always have unit 278 // MinLatency. MinLatency > 0 is for in-order processors with varying min 280 if (SchedModel.MinLatency != 0) 283 // MinLatency == 0 indicates an out-of-order processor that can dispatch
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H A D | MachineScheduler.cpp | 350 /// FIXME: Adjust SuccSU height based on MinLatency. 384 /// FIXME: Adjust PredSU height based on MinLatency. 1464 unsigned MinLatency = I->getMinLatency(); local 1466 Top.MaxMinLatency = std::max(MinLatency, Top.MaxMinLatency); 1468 if (SU->TopReadyCycle < PredReadyCycle + MinLatency) 1469 SU->TopReadyCycle = PredReadyCycle + MinLatency; 1485 unsigned MinLatency = I->getMinLatency(); local 1487 Bot.MaxMinLatency = std::max(MinLatency, Bot.MaxMinLatency); 1489 if (SU->BotReadyCycle < SuccReadyCycle + MinLatency) 1490 SU->BotReadyCycle = SuccReadyCycle + MinLatency; [all...] |
H A D | TargetInstrInfo.cpp | 638 // still have a MinLatency property, which getStageLatency checks. 681 // If MinLatency is valid, call getInstrLatency. This uses Stage latency if 682 // it exists before defaulting to MinLatency. 683 if (ItinData->SchedModel->MinLatency >= 0) 686 // If MinLatency is invalid, OperandLatency is interpreted as MinLatency.
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/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | ScheduleDAG.h | 93 /// Record MinLatency seperately from "expected" Latency. 97 unsigned MinLatency; member in class:llvm::SDep 123 MinLatency = Latency; 126 : Dep(S, Order), Contents(), Latency(0), MinLatency(0) { 146 && Latency == Other.Latency && MinLatency == Other.MinLatency; 170 return MinLatency; 175 MinLatency = Lat;
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