Searched refs:MTCTR (Results 1 - 6 of 6) sorted by relevance

/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp181 // Do not allow MTCTR and BCTRL to be in the same dispatch group.
211 if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true;
H A DPPCISelLowering.h107 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
108 /// MTCTR instruction.
109 MTCTR, enumerator in enum:llvm::PPCISD::NodeType
H A DPPCCTRLoops.cpp727 TII->get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(CountReg,
H A DPPCAsmPrinter.cpp939 OutStreamer.EmitInstruction(MCInstBuilder(PPC::MTCTR).addReg(PPC::R12));
994 OutStreamer.EmitInstruction(MCInstBuilder(PPC::MTCTR).addReg(PPC::R12));
H A DPPCISelDAGToDAG.cpp1271 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
H A DPPCISelLowering.cpp632 case PPCISD::MTCTR: return "PPCISD::MTCTR";
3246 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3317 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
4103 // Check if this is an indirect call (MTCTR/BCTRL).
4118 // mean the MTCTR instruction must use R12; it's easier to model this
4462 // not mean the MTCTR instruction must use R12; it's easier to model this as
6240 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);

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