Searched refs:LIS (Results 1 - 25 of 36) sorted by relevance

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/freebsd-10.0-release/contrib/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp40 LiveInterval &LI = LIS.getOrCreateInterval(VReg);
62 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def);
95 LiveInterval &li = LIS.getInterval(MO.getReg());
124 DefIdx = LIS.getInstructionIndex(RM.OrigMI);
127 RM.OrigMI = LIS.getInstructionFromIndex(DefIdx);
151 return LIS.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late)
157 LIS.removeInterval(Reg);
190 LIS.getInstructionIndex(DefMI),
191 LIS.getInstructionIndex(UseMI)))
211 LIS
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H A DRegAllocBase.h64 LiveIntervals *LIS; member in class:llvm::RegAllocBase
68 RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0), Matrix(0) {}
H A DPHIElimination.cpp52 LiveIntervals *LIS; member in class:__anon2190::PHIElimination
129 LIS = getAnalysisIfAvailable<LiveIntervals>();
138 if (!DisableEdgeSplitting && (LV || LIS)) {
157 if (LIS)
158 LIS->RemoveMachineInstrFromMaps(DefMI);
166 if (LIS)
167 LIS->RemoveMachineInstrFromMaps(I->first);
304 if (LIS) {
306 SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(NewInstr);
308 SlotIndex MBBStartIndex = LIS
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H A DLiveDebugVariables.cpp129 LiveIntervals &LIS, const TargetInstrInfo &TII);
223 /// @param LIS Live intervals analysis.
228 LiveIntervals &LIS, MachineDominatorTree &MDT,
242 LiveIntervals &LIS);
247 LiveIntervals &LIS, MachineDominatorTree &MDT,
260 LiveIntervals &LIS, const TargetInstrInfo &TRI);
280 LiveIntervals *LIS; member in class:__anon2162::LDVImpl
474 LIS->getMBBStartIdx(MBB) :
475 LIS->getInstructionIndex(llvm::prior(MBBI)).getRegSlot();
492 LiveIntervals &LIS, MachineDominatorTre
489 extendDef(SlotIndex Idx, unsigned LocNo, LiveInterval *LI, const VNInfo *VNI, SmallVectorImpl<SlotIndex> *Kills, LiveIntervals &LIS, MachineDominatorTree &MDT, UserValueScopes &UVS) argument
551 addDefsFromCopies(LiveInterval *LI, unsigned LocNo, const SmallVectorImpl<SlotIndex> &Kills, SmallVectorImpl<std::pair<SlotIndex, unsigned> > &NewDefs, MachineRegisterInfo &MRI, LiveIntervals &LIS) argument
624 computeIntervals(MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, LiveIntervals &LIS, MachineDominatorTree &MDT, UserValueScopes &UVS) argument
890 findInsertLocation(MachineBasicBlock *MBB, SlotIndex Idx, LiveIntervals &LIS) argument
916 insertDebugValue(MachineBasicBlock *MBB, SlotIndex Idx, unsigned LocNo, LiveIntervals &LIS, const TargetInstrInfo &TII) argument
939 emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS, const TargetInstrInfo &TII) argument
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H A DRegisterCoalescer.cpp84 LiveIntervals *LIS; member in class:__anon2204::RegisterCoalescer
401 LiveRangeEdit(0, NewRegs, *MF, *LIS, 0, this).eliminateDeadDefs(DeadDefs);
431 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
433 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
434 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
456 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
470 LIS->getInstructionFromIndex(ValLR->end.getPrevSlot());
509 LIS->shrinkToUses(&IntA);
523 if (LIS->hasPHIKill(IntA, AValNo))
572 SlotIndex CopyIdx = LIS
1231 LiveIntervals *LIS; member in class:__anon2205::JoinVals
2011 isLocalCopy(MachineInstr *Copy, const LiveIntervals *LIS) argument
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H A DInlineSpiller.cpp56 LiveIntervals &LIS; member in class:__anon2158::InlineSpiller
140 LIS(pass.getAnalysis<LiveIntervals>()),
232 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
282 LiveInterval &SnipLI = LIS.getInterval(SnipReg);
368 SV.SpillMBB = LIS.getMBBFromIndex(SV.SpillVNI->def);
386 DepSV.SpillMBB = LIS.getMBBFromIndex(DepSV.SpillVNI->def);
526 LiveInterval &LI = LIS.getInterval(Reg);
527 LiveInterval &OrigLI = LIS.getInterval(Original);
572 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
578 LiveInterval &SrcLI = LIS
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H A DCalcSpillWeights.cpp46 LiveIntervals &LIS = getAnalysis<LiveIntervals>(); local
48 VirtRegAuxInfo VRAI(MF, LIS, getAnalysis<MachineLoopInfo>());
53 VRAI.CalculateWeightAndHint(LIS.getInterval(Reg));
91 const LiveIntervals &LIS,
101 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
104 if (!TII.isTriviallyReMaterializable(MI, LIS.getAliasAnalysis()))
153 if (writes && isExiting && LIS.isLiveOutOfMBB(li, mbb))
189 if (li.isZeroLength(LIS.getSlotIndexes())) {
198 if (isRematerializable(li, LIS, *MF.getTarget().getInstrInfo()))
90 isRematerializable(const LiveInterval &LI, const LiveIntervals &LIS, const TargetInstrInfo &TII) argument
H A DRegAllocBase.cpp59 LIS = &lis;
74 enqueue(&LIS->getInterval(Reg));
90 LIS->removeInterval(VirtReg->reg);
135 LIS->removeInterval(SplitVirtReg->reg);
H A DTwoAddressInstructionPass.cpp76 LiveIntervals *LIS; member in class:__anon2240::TwoAddressInstructionPass
172 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
215 if (LIS) {
216 LiveInterval &LI = LIS->getInterval(SavedReg);
220 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
226 KillMI = LIS->getInstructionFromIndex(I->end);
276 if (MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))) {
289 if (!LIS) {
303 if (LIS)
360 isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS) argument
402 isKilled(MachineInstr &MI, unsigned Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives) argument
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H A DSplitKit.cpp47 LIS(lis),
65 SlotIndex MBBEnd = LIS.getMBBEndIdx(MBB);
74 LSP.first = LIS.getInstructionIndex(FirstTerm);
85 LSP.second = LIS.getInstructionIndex(I);
93 if (!LPad || !LSP.second || !LIS.isLiveInToMBB(*CurLI, LPad))
116 if (LSP == LIS.getMBBEndIdx(MBB))
118 return LIS.getInstructionFromIndex(LSP);
138 UseSlots.push_back(LIS.getInstructionIndex(&*I).getRegSlot());
155 const_cast<LiveIntervals&>(LIS)
186 MachineFunction::iterator MFI = LIS
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H A DInterferenceCache.h57 /// LIS - Used for accessing register mask interference maps.
58 LiveIntervals *LIS; member in class:llvm::InterferenceCache::Entry
96 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0), LIS(0) {}
103 LIS = lis;
H A DLiveRegMatrix.cpp52 LIS = &getAnalysis<LiveIntervals>();
108 LIS->checkRegMaskInterference(VirtReg, RegMaskUsable);
123 if (VirtReg.overlaps(LIS->getRegUnit(*Units), CP, *LIS->getSlotIndexes()))
H A DVirtRegMap.cpp160 LiveIntervals *LIS; member in class:__anon2243::VirtRegRewriter
208 LIS = &getAnalysis<LiveIntervals>();
216 LIS->addKillFlags(VRM);
242 LiveInterval &LI = LIS->getInterval(VirtReg);
243 if (LI.empty() || LIS->intervalIsInOneMBB(LI))
H A DLiveIntervalAnalysis.cpp710 LiveIntervals& LIS; member in class:LiveIntervals::HMEditor
719 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI, argument
722 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),
731 return &LIS.getRegUnit(Unit);
732 return LIS.getCachedRegUnit(Unit);
754 updateRange(LIS.getInterval(Reg));
827 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(I->end))
960 std::lower_bound(LIS.RegMaskSlots.begin(), LIS
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H A DRegisterPressure.cpp192 return &LIS->getInterval(Reg);
193 return LIS->getCachedRegUnit(Reg);
213 LIS = lis;
253 return LIS->getMBBEndIdx(MBB);
254 return LIS->getInstructionIndex(IdxPos).getRegSlot();
425 SlotIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
677 const LiveIntervals *LIS) {
684 SlotIndex InstSlot = LIS->getInstructionIndex(MI).getRegSlot();
708 SlotIdx = LIS->getInstructionIndex(MI).getRegSlot();
718 && !findUseBetween(Reg, CurrIdx, SlotIdx, MRI, LIS)) {
674 findUseBetween(unsigned Reg, SlotIndex PriorUseIdx, SlotIndex NextUseIdx, const MachineRegisterInfo *MRI, const LiveIntervals *LIS) argument
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H A DInterferenceCache.cpp90 RegUnits.back().Fixed = &LIS->getRegUnit(*Units);
163 RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum);
164 RegMaskBits = LIS->getRegMaskBitsInBlock(MBBNum);
H A DRegAllocBasic.cpp203 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM);
262 LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM);
H A DSplitKit.h45 const LiveIntervals &LIS; member in class:llvm::SplitAnalysis
212 LiveIntervals &LIS; member in class:llvm::SplitEditor
H A DRegAllocGreedy.cpp354 Matrix->unassign(LIS->getInterval(VirtReg));
367 LiveInterval &LI = LIS->getInterval(VirtReg);
425 LiveInterval *LI = &LIS->getInterval(~Queue.top().second);
1206 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1254 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1309 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1409 const LiveInterval &LI = LIS->getRegUnit(*Units);
1464 ArrayRef<SlotIndex> RMS = LIS->getRegMaskSlotsInBlock(BI.MBB->getNumber());
1619 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1665 if (LIS
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/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/
H A DCalcSpillWeights.h44 LiveIntervals &LIS; member in class:llvm::VirtRegAuxInfo
50 MF(mf), LIS(lis), Loops(loops) {}
H A DRegisterPressure.h174 const LiveIntervals *LIS; member in class:llvm::RegPressureTracker
183 /// or RegisterPressure. If requireIntervals is false, LIS are ignored.
199 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(true) {}
202 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(false) {}
H A DScheduleDAGInstrs.h76 LiveIntervals *LIS; member in class:llvm::ScheduleDAGInstrs
149 LiveIntervals *LIS = 0);
154 LiveIntervals *getLIS() const { return LIS; }
H A DLiveRangeEdit.h61 LiveIntervals &LIS; member in class:llvm::LiveRangeEdit
109 MRI(MF.getRegInfo()), LIS(lis), VRM(vrm),
189 /// to erase it from LIS.
H A DLiveRegMatrix.h43 LiveIntervals *LIS; member in class:llvm::LiveRegMatrix
H A DMachineScheduler.h56 LiveIntervals *LIS; member in struct:llvm::MachineSchedContext
256 ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),

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