/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMFeatures.h | 21 bool IsCPSRDead(const InstrType *Instr); 24 inline bool isV8EligibleForIT(const InstrType *Instr) { argument 25 switch (Instr->getOpcode()) { 52 return IsCPSRDead(Instr); 79 return Instr->getOperand(2).getReg() != ARM::PC; 84 return Instr->getOperand(0).getReg() != ARM::PC; 86 return Instr->getOperand(0).getReg() != ARM::PC && 87 Instr->getOperand(2).getReg() != ARM::PC; 90 return Instr->getOperand(0).getReg() != ARM::PC && 91 Instr [all...] |
H A D | MVETPAndVPTOptimisationsPass.cpp | 76 MachineInstr &Instr, 574 static ARMCC::CondCodes GetCondCode(MachineInstr &Instr) { argument 575 assert(IsVCMP(Instr.getOpcode()) && "Inst must be a VCMP"); 576 return ARMCC::CondCodes(Instr.getOperand(3).getImm()); 606 // Returns true if Instr writes to VCCR. 607 static bool IsWritingToVCCR(MachineInstr &Instr) { argument 608 if (Instr.getNumOperands() == 0) 610 MachineOperand &Dst = Instr.getOperand(0); 616 MachineRegisterInfo &RegInfo = Instr.getMF()->getRegInfo(); 622 // <Instr tha 629 ReplaceRegisterUseWithVPNOT( MachineBasicBlock &MBB, MachineInstr &Instr, MachineOperand &User, Register Target) argument 986 << Instr); local [all...] |
H A D | Thumb1InstrInfo.cpp | 144 unsigned Instr; local 146 Instr = ARM::tLDRLIT_ga_pcrel; 148 Instr = ARM::t2MOVi32imm; 150 Instr = ARM::tMOVi32imm; 152 Instr = ARM::tLDRLIT_ga_abs; 153 expandLoadStackGuardBase(MI, Instr, ARM::tLDRi);
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/ |
H A D | LanaiDisassembler.h | 30 getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes,
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H A D | LanaiDisassembler.cpp | 90 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { argument 94 if (isRMOpcode(Instr.getOpcode())) 96 else if (isSPLSOpcode(Instr.getOpcode())) 98 else if (isRRMOpcode(Instr.getOpcode())) { 112 if (Instr.getOperand(2).isReg()) { 113 Instr.getOperand(2).setReg(Lanai::R0); 115 if (Instr.getOperand(2).isImm()) 116 Instr.getOperand(2).setImm(0); 127 Instr.addOperand(MCOperand::createImm(AluOp)); 132 LanaiDisassembler::getInstruction(MCInst &Instr, uint64_ argument [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | CorrelatedValuePropagation.cpp | 681 static bool narrowSDivOrSRem(BinaryOperator *Instr, const ConstantRange &LCR, argument 683 assert(Instr->getOpcode() == Instruction::SDiv || 684 Instr->getOpcode() == Instruction::SRem); 685 assert(!Instr->getType()->isVectorTy()); 687 // Find the smallest power of two bitwidth that's sufficient to hold Instr's 689 unsigned OrigWidth = Instr->getType()->getIntegerBitWidth(); 711 IRBuilder<> B{Instr}; 712 auto *TruncTy = Type::getIntNTy(Instr->getContext(), NewWidth); 713 auto *LHS = B.CreateTruncOrBitCast(Instr->getOperand(0), TruncTy, 714 Instr 728 expandUDivOrURem(BinaryOperator *Instr, const ConstantRange &XCR, const ConstantRange &YCR) argument 809 narrowUDivOrURem(BinaryOperator *Instr, const ConstantRange &XCR, const ConstantRange &YCR) argument 847 processUDivOrURem(BinaryOperator *Instr, LazyValueInfo *LVI) argument 980 processSDivOrSRem(BinaryOperator *Instr, LazyValueInfo *LVI) argument [all...] |
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | DbgEntityHistoryCalculator.h | 78 Entry(const MachineInstr *Instr, EntryKind Kind) argument 79 : Instr(Instr, Kind), EndIndex(NoEntry) {} 81 const MachineInstr *getInstr() const { return Instr.getPointer(); } 83 EntryKind getEntryKind() const { return Instr.getInt(); } 92 PointerIntPair<const MachineInstr *, 1, EntryKind> Instr; member in class:llvm::DbgValueHistoryMap::Entry
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/freebsd-current/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/ |
H A D | ELF_aarch64.cpp | 193 uint32_t Instr = *(const ulittle32_t *)FixupContent; local 194 if (!aarch64::isADR(Instr)) 210 uint32_t Instr = *(const ulittle32_t *)FixupContent; local 211 if (!aarch64::isLoadStoreImm12(Instr) || 212 aarch64::getPageOffset12Shift(Instr) != 0) 221 uint32_t Instr = *(const ulittle32_t *)FixupContent; local 222 if (!aarch64::isLoadStoreImm12(Instr) || 223 aarch64::getPageOffset12Shift(Instr) != 1) 232 uint32_t Instr = *(const ulittle32_t *)FixupContent; local 233 if (!aarch64::isLoadStoreImm12(Instr) || 243 uint32_t Instr = *(const ulittle32_t *)FixupContent; local 254 uint32_t Instr = *(const ulittle32_t *)FixupContent; local 265 uint32_t Instr = *(const ulittle32_t *)FixupContent; local 276 uint32_t Instr = *(const ulittle32_t *)FixupContent; local 287 uint32_t Instr = *(const ulittle32_t *)FixupContent; local 298 uint32_t Instr = *(const ulittle32_t *)FixupContent; local 309 uint32_t Instr = *(const ulittle32_t *)FixupContent; local 318 uint32_t Instr = *(const ulittle32_t *)FixupContent; local [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600OptimizeVectorRegisters.cpp | 51 MachineInstr *Instr; member in class:__anon2206::RegSeqInfo 55 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { 57 for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) { 58 MachineOperand &MO = Instr->getOperand(i); 59 unsigned Chan = Instr->getOperand(i + 1).getImm(); 70 return RSI.Instr == Instr; 184 Register Reg = RSI->Instr->getOperand(0).getReg(); 185 MachineBasicBlock::iterator Pos = RSI->Instr; 189 Register SrcVec = BaseRSI->Instr [all...] |
/freebsd-current/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/ |
H A D | aarch64.h | 354 // Returns whether the Instr is LD/ST (imm12) 355 inline bool isLoadStoreImm12(uint32_t Instr) { argument 357 return (Instr & LoadStoreImm12Mask) == 0x39000000; 360 inline bool isTestAndBranchImm14(uint32_t Instr) { argument 362 return (Instr & TestAndBranchImm14Mask) == 0x36000000; 365 inline bool isCondBranchImm19(uint32_t Instr) { argument 367 return (Instr & CondBranchImm19Mask) == 0x54000000; 370 inline bool isCompAndBranchImm19(uint32_t Instr) { argument 372 return (Instr & CompAndBranchImm19Mask) == 0x34000000; 375 inline bool isADR(uint32_t Instr) { argument 386 getPageOffset12Shift(uint32_t Instr) argument 402 isMoveWideImm16(uint32_t Instr) argument 411 getMoveWide16Shift(uint32_t Instr) argument [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/BPF/Disassembler/ |
H A D | BPFDisassembler.cpp | 68 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 165 DecodeStatus BPFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, argument 182 Result = decodeInstruction(DecoderTableBPFALU3264, Instr, Insn, Address, 185 Result = decodeInstruction(DecoderTableBPF64, Instr, Insn, Address, this, 190 switch (Instr.getOpcode()) { 202 auto& Op = Instr.getOperand(1); 212 auto Op = Instr.getOperand(0); 213 Instr.clear(); 214 Instr.addOperand(MCOperand::createReg(BPF::R6)); 215 Instr [all...] |
/freebsd-current/contrib/llvm-project/llvm/include/llvm/Analysis/ |
H A D | VectorUtils.h | 450 InterleaveGroup(InstTy *Instr, int32_t Stride, Align Alignment) argument 451 : Alignment(Alignment), InsertPos(Instr) { 456 Members[0] = Instr; 464 /// Try to insert a new member \p Instr with index \p Index and 469 bool insertMember(InstTy *Instr, int32_t Index, Align NewAlign) { 507 Members[Key] = Instr; 521 uint32_t getIndex(const InstTy *Instr) const { 523 if (I.second == Instr) 622 /// Check if \p Instr belongs to any interleave group. 623 bool isInterleaved(Instruction *Instr) cons 706 createInterleaveGroup(Instruction *Instr, int Stride, Align Alignment) argument [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | RemoveRedundantDebugValues.cpp | 138 for (auto &Instr : DbgValsToBeRemoved) { 139 LLVM_DEBUG(dbgs() << "removing "; Instr->dump()); 140 Instr->eraseFromParent(); 193 for (auto &Instr : DbgValsToBeRemoved) { 194 LLVM_DEBUG(dbgs() << "removing "; Instr->dump()); 195 Instr->eraseFromParent();
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H A D | MachineSSAContext.cpp | 87 if (auto *Instr = MRI->getUniqueVRegDef(Value)) { 89 Instr->print(Out);
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H A D | MachineUniformityAnalysis.cpp | 32 const MachineInstr &Instr) { 37 for (auto &op : Instr.all_defs()) { 79 const MachineInstr &Instr) { 80 assert(!isAlwaysUniform(Instr)); 81 if (Instr.isTerminator()) 83 for (const MachineOperand &op : Instr.all_defs()) { 31 markDefsDivergent( const MachineInstr &Instr) argument 78 pushUsers( const MachineInstr &Instr) argument
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/freebsd-current/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | UniformityAnalysis.cpp | 29 const Instruction &Instr) { 30 return markDivergent(cast<Value>(&Instr)); 59 const Instruction &Instr) { 60 assert(!isAlwaysUniform(Instr)); 61 if (Instr.isTerminator()) 63 pushUsers(cast<Value>(&Instr)); 28 markDefsDivergent( const Instruction &Instr) argument 58 pushUsers( const Instruction &Instr) argument
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXProxyRegErasure.cpp | 56 void replaceRegisterUsage(MachineInstr &Instr, MachineOperand &From, 107 void NVPTXProxyRegErasure::replaceRegisterUsage(MachineInstr &Instr, argument 110 for (auto &Op : Instr.uses()) {
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H A D | NVPTXImageOptimizer.cpp | 63 for (Instruction &Instr : BB) { 64 if (CallInst *CI = dyn_cast<CallInst>(&Instr)) { 71 Changed |= replaceIsTypePSampler(Instr); 74 Changed |= replaceIsTypePSurface(Instr); 77 Changed |= replaceIsTypePTexture(Instr);
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.h | 31 getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes,
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64PromoteConstant.cpp | 272 static bool shouldConvertUse(const Constant *Cst, const Instruction *Instr, 276 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2) 280 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0) 284 if (isa<const InsertValueInst>(Instr) && OpIdx > 1) 287 if (isa<const AllocaInst>(Instr) && OpIdx > 0) 291 if (isa<const LoadInst>(Instr) && OpIdx > 0) 295 if (isa<const StoreInst>(Instr) && OpIdx > 1) 299 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0) 304 if (isa<const LandingPadInst>(Instr)) 308 if (isa<const SwitchInst>(Instr)) [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/IR/ |
H A D | FPEnv.cpp | 90 Intrinsic::ID getConstrainedIntrinsicID(const Instruction &Instr) { argument 92 switch (Instr.getOpcode()) { 110 if (auto *IntrinCall = dyn_cast<IntrinsicInst>(&Instr)) {
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H A D | SSAContext.cpp | 66 bool SSAContext::isConstantOrUndefValuePhi(const Instruction &Instr) { argument 67 if (auto *Phi = dyn_cast<PHINode>(&Instr))
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H A D | DiagnosticInfo.cpp | 54 : DiagnosticInfo(DK_InlineAsm, Severity), MsgStr(MsgStr), Instr(&I) {
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/freebsd-current/contrib/llvm-project/llvm/include/llvm/IR/ |
H A D | FPEnv.h | 73 Intrinsic::ID getConstrainedIntrinsicID(const Instruction &Instr);
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/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | RegBankSelect.h | 207 MachineInstr &Instr; member in class:llvm::RegBankSelect::InstrInsertPoint 209 /// Does the insertion point is before or after Instr. 216 return Instr; 217 return Instr.getNextNode() ? *Instr.getNextNode() 218 : Instr.getParent()->end(); 222 return *Instr.getParent(); 226 /// Create an insertion point before (\p Before=true) or after \p Instr. 227 InstrInsertPoint(MachineInstr &Instr, bool Before = true);
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