Searched refs:EVERGREEN_CRTC5_REGISTER_OFFSET (Results 1 - 6 of 6) sorted by relevance

/freebsd-10.0-release/sys/dev/drm2/radeon/
H A Devergreen_reg.h218 #define EVERGREEN_CRTC5_REGISTER_OFFSET (0x129f0 - 0x6df0) macro
H A Devergreen.c48 EVERGREEN_CRTC5_REGISTER_OFFSET
2497 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2508 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2566 afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2706 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2717 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2732 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
2755 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2763 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2797 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEA
[all...]
H A Dsi.c3296 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3307 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3524 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
3535 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
3566 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
3601 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3607 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
3609 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
H A Dradeon_display.c1292 rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1604 EVERGREEN_CRTC5_REGISTER_OFFSET);
1606 EVERGREEN_CRTC5_REGISTER_OFFSET);
H A Dradeon_device.c451 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
H A Datombios_crtc.c1923 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;

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