Searched refs:EVERGREEN_CRTC3_REGISTER_OFFSET (Results 1 - 6 of 6) sorted by relevance

/freebsd-10.0-release/sys/dev/drm2/radeon/
H A Devergreen_reg.h216 #define EVERGREEN_CRTC3_REGISTER_OFFSET (0x111f0 - 0x6df0) macro
H A Devergreen.c46 EVERGREEN_CRTC3_REGISTER_OFFSET,
2493 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2504 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2564 afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2702 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2713 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2730 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
2751 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2761 rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2782 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEA
[all...]
H A Dsi.c3292 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3303 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3520 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
3531 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
3562 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
3586 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3592 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
3594 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
H A Dradeon_display.c1280 rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1590 EVERGREEN_CRTC3_REGISTER_OFFSET);
1592 EVERGREEN_CRTC3_REGISTER_OFFSET);
H A Dradeon_device.c449 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
H A Datombios_crtc.c1917 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;

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