Searched refs:CP_PACKET3 (Results 1 - 13 of 13) sorted by relevance
/freebsd-10.0-release/sys/dev/drm2/radeon/ |
H A D | r600_blit.c | 66 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 69 OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0)); 73 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 78 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 82 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 86 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 90 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 94 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 98 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 119 OUT_RING(CP_PACKET3(R600_IT_SURFACE_SYN [all...] |
H A D | radeon_state.c | 797 OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); 940 OUT_RING(CP_PACKET3 962 OUT_RING(CP_PACKET3 1069 OUT_RING(CP_PACKET3 1092 OUT_RING(CP_PACKET3 1120 OUT_RING(CP_PACKET3 1143 OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2)); 1260 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12)); 1332 OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13)); 1564 OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRI [all...] |
H A D | r300d.h | 43 #define CP_PACKET3 0xC0000000 macro 67 #define PACKET3(op, n) (CP_PACKET3 | \
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H A D | radeon_drv.h | 1919 #define CP_PACKET3( pkt, n ) \ macro 2037 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2043 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2049 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
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H A D | r300_cmdbuf.c | 447 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); 622 *cmd != CP_PACKET3(RADEON_CP_INDX_BUFFER, 2)) {
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H A D | rv515d.h | 186 #define CP_PACKET3 0xC0000000 macro 207 #define PACKET3(op, n) (CP_PACKET3 | \
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H A D | r600_cp.c | 2297 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); 2300 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); 2319 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); 2391 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
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H A D | r100d.h | 43 #define CP_PACKET3 0xC0000000 macro 66 #define PACKET3(op, n) (CP_PACKET3 | \
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/freebsd-10.0-release/sys/dev/drm/ |
H A D | r600_blit.c | 1220 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 1223 OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0)); 1227 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 1232 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 1236 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 1240 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 1244 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 1248 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 1252 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 1273 OUT_RING(CP_PACKET3(R600_IT_SURFACE_SYN [all...] |
H A D | radeon_state.c | 774 OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); 909 OUT_RING(CP_PACKET3 931 OUT_RING(CP_PACKET3 1038 OUT_RING(CP_PACKET3 1061 OUT_RING(CP_PACKET3 1089 OUT_RING(CP_PACKET3 1112 OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2)); 1229 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12)); 1301 OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13)); 1529 OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRI [all...] |
H A D | radeon_drv.h | 1899 #define CP_PACKET3( pkt, n ) \ macro 2028 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2034 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2040 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
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H A D | r300_cmdbuf.c | 461 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); 639 cmd[0] != CP_PACKET3(RADEON_CP_INDX_BUFFER, 2)) {
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H A D | r600_cp.c | 2133 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); 2136 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); 2155 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); 2227 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
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