Searched refs:CC1 (Results 1 - 5 of 5) sorted by relevance

/freebsd-10.0-release/contrib/gcc/config/s390/
H A Ds390.c474 CC1 and CC2 for mixed selected bits (TMxx), it is false
496 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
824 const int CC1 = 1 << 2; local
839 case NE: return CC1 | CC2 | CC3;
847 case EQ: return CC1;
857 case NE: return CC0 | CC1 | CC3;
866 case NE: return CC0 | CC1 | CC2;
875 case NE: return CC1 | CC3;
884 case GEU: return CC0 | CC1; /* no carry */
892 case GTU: return CC0 | CC1; /* borro
[all...]
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp1606 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1615 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1620 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1639 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1664 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1665 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1668 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1669 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
H A DDAGCombiner.cpp2431 SDValue LL, LR, RL, RR, CC0, CC1; local
2599 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2601 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3045 SDValue LL, LR, RL, RR, CC0, CC1; local
3114 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3116 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp495 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
497 if (CC1 == CC2)
500 switch (CC1) {
/freebsd-10.0-release/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp9297 unsigned CC0, CC1; local
9300 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9303 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9309 DAG.getConstant(CC1, MVT::i8));

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