/freebsd-10-stable/sys/dev/drm2/ |
H A D | drm_dp_helper.c | 45 int lane) 47 int i = DP_LANE0_1_STATUS + (lane >> 1); 48 int s = (lane & 1) * 4; 58 int lane; local 64 for (lane = 0; lane < lane_count; lane++) { 65 lane_status = dp_get_lane_status(link_status, lane); 76 int lane; local 79 for (lane 44 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE], int lane) argument 88 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], int lane) argument 101 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], int lane) argument [all...] |
H A D | drm_dp_helper.h | 333 int lane); 335 int lane);
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/freebsd-10-stable/sys/contrib/octeon-sdk/ |
H A D | cvmx-qlm.h | 107 * @param lane Lane in QLM to get 112 extern uint64_t cvmx_qlm_jtag_get(int qlm, int lane, const char *name); 118 * @param lane Lane in QLM to set, or -1 for all lanes 122 extern void cvmx_qlm_jtag_set(int qlm, int lane, const char *name, uint64_t value);
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H A D | cvmx-helper-errata.c | 304 int lane; local 313 for (lane=0; lane<4; lane++) 315 /* Each lane has 268 bits. We need to set cfg_cdr_incx<67:64>=3 and
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H A D | cvmx-qlm.c | 77 * new data => lane 3 => lane 2 => lane 1 => lane 0 => data out 82 * new data => lane 0 => lane 1 => lane 2 => lane 3 => data out 322 * @param lane Lane in QLM to get 327 uint64_t cvmx_qlm_jtag_get(int qlm, int lane, cons argument 353 cvmx_qlm_jtag_set(int qlm, int lane, const char *name, uint64_t value) argument [all...] |
/freebsd-10-stable/sys/gnu/dts/arm/ |
H A D | armada-xp-mv78260.dtsi | 145 marvell,pcie-lane = <0>; 162 marvell,pcie-lane = <1>; 179 marvell,pcie-lane = <2>; 196 marvell,pcie-lane = <3>; 213 marvell,pcie-lane = <0>; 230 marvell,pcie-lane = <1>; 247 marvell,pcie-lane = <2>; 264 marvell,pcie-lane = <3>; 281 marvell,pcie-lane = <0>;
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H A D | armada-385.dtsi | 121 marvell,pcie-lane = <0>; 139 marvell,pcie-lane = <0>; 157 marvell,pcie-lane = <0>; 178 marvell,pcie-lane = <0>;
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H A D | armada-380.dtsi | 110 marvell,pcie-lane = <0>; 128 marvell,pcie-lane = <0>; 146 marvell,pcie-lane = <0>;
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H A D | armada-xp-mv78230.dtsi | 129 marvell,pcie-lane = <0>; 146 marvell,pcie-lane = <1>; 163 marvell,pcie-lane = <2>; 180 marvell,pcie-lane = <3>; 197 marvell,pcie-lane = <0>;
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H A D | armada-xp-mv78460.dtsi | 166 marvell,pcie-lane = <0>; 183 marvell,pcie-lane = <1>; 200 marvell,pcie-lane = <2>; 217 marvell,pcie-lane = <3>; 234 marvell,pcie-lane = <0>; 251 marvell,pcie-lane = <1>; 268 marvell,pcie-lane = <2>; 285 marvell,pcie-lane = <3>; 302 marvell,pcie-lane = <0>; 319 marvell,pcie-lane [all...] |
H A D | armada-370.dtsi | 104 marvell,pcie-lane = <0>; 121 marvell,pcie-lane = <0>;
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H A D | armada-375.dtsi | 588 marvell,pcie-lane = <0>; 605 marvell,pcie-lane = <1>;
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H A D | exynos5250-smdk5250.dts | 83 samsung,lane-count = <4>;
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H A D | exynos5250-arndale.dts | 127 samsung,lane-count = <4>;
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H A D | exynos5250-spring.dts | 76 samsung,lane-count = <1>;
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H A D | exynos5420-smdk5420.dts | 109 samsung,lane-count = <4>;
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/freebsd-10-stable/sys/dev/drm2/radeon/ |
H A D | atombios_dp.c | 304 int lane; local 306 for (lane = 0; lane < lane_count; lane++) { 307 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 308 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 310 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", 311 lane, 331 for (lane = 0; lane < [all...] |
/freebsd-10-stable/contrib/ofed/management/opensm/opensm/ |
H A D | osm_ucast_lash.c | 95 unsigned lane; member in struct:_switch::routing_table 205 int dest_switch, int lane) 218 v = cdg_vertex_matrix[lane][sw][i_next_switch]; 223 cdg_vertex_matrix[lane][sw][i_next_switch] = NULL; 237 cdg_vertex_matrix[lane][i_next_switch] 357 int lane) 370 if (cdg_vertex_matrix[lane][sw][next_switch] == NULL) { 389 cdg_vertex_matrix[lane][sw][next_switch] = v; 391 v = cdg_vertex_matrix[lane][sw][next_switch]; 430 int dest_switch, int lane) 204 remove_semipermanent_depend_for_sp(lash_t * p_lash, int sw, int dest_switch, int lane) argument 356 generate_cdg_for_sp(lash_t * p_lash, int sw, int dest_switch, int lane) argument 429 set_temp_depend_to_permanent_for_sp(lash_t * p_lash, int sw, int dest_switch, int lane) argument 459 remove_temp_depend_for_sp(lash_t * p_lash, int sw, int dest_switch, int lane) argument [all...] |
/freebsd-10-stable/sys/dev/drm2/i915/ |
H A D | intel_dp.c | 197 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 693 DRM_DEBUG_KMS("DP link computation with max lane count %i " 711 DRM_DEBUG_KMS("DP link bw %02x lane " 772 * Find the lane count in the intel_encoder private 1377 int lane) 1379 int s = ((lane & 1) ? 1382 uint8_t l = adjust_request[lane>>1]; 1389 int lane) 1391 int s = ((lane & 1) ? 1394 uint8_t l = adjust_request[lane>> 1376 intel_get_adjust_request_voltage(uint8_t adjust_request[2], int lane) argument 1388 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2], int lane) argument 1465 int lane; local 1590 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane) argument 1603 int lane; local 1623 int lane; local [all...] |
H A D | intel_display.c | 4364 int target_clock, pixel_multiplier, lane, link_bw, factor; local 4458 lane = 0; 4463 intel_edp_link_config(edp_encoder, &lane, &link_bw); 4476 * Hence the bw of each lane in terms of the mode signal 4510 if (!lane) { 4517 lane = bps / (link_bw * 8) + 1; 4520 intel_crtc->fdi_lanes = lane; 4524 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
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/freebsd-10-stable/sys/dev/bxe/ |
H A D | bxe_elink.c | 2610 /* Use lane 1 (of lanes 0-3) */ 2619 /* Use lane 1 (of lanes 0-3) */ 4046 uint8_t lane = 0; local 4077 lane = (port<<1) + path; 4092 lane = path << 1 ; 4094 return lane; 4113 /* In Dual-lane mode, two lanes are joined together, 4370 uint8_t lane = elink_get_warpcore_lane(phy, params); local 4377 lane; 4436 * i.e. reset the lane (i 4552 uint16_t lane = elink_get_warpcore_lane(phy, params); local 4565 uint16_t lane, i, cl72_ctrl, an_adv = 0, val; local 4719 uint16_t val16, i, lane; local 4787 uint16_t misc1_val, tap_val, tx_driver_val, lane, val; local 4970 elink_warpcore_set_20G_DXGXS(struct bxe_softc *sc, struct elink_phy *phy, uint16_t lane) argument 5126 elink_warpcore_clear_regs(struct elink_phy *phy, struct elink_params *params, uint16_t lane) argument 5222 uint16_t gp2_status_reg0, lane; local 5247 uint16_t lane = elink_get_warpcore_lane(phy, params); local 5289 uint16_t lane = elink_get_warpcore_lane(phy, params); local 5331 uint16_t lane = elink_get_warpcore_lane(phy, params); local 5436 uint16_t val16, lane; local 5492 uint32_t lane; local 6542 uint8_t lane; local 7345 uint8_t lane = elink_get_warpcore_lane(int_phy, params); local 9536 uint8_t lane = elink_get_warpcore_lane(phy, params); local 14894 uint16_t base_page, next_page, not_kr2_device, lane; local [all...] |
/freebsd-10-stable/usr.sbin/tcpdump/tcpdump/ |
H A D | Makefile | 73 print-lane.c \
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/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 764 // Add the lane 1114 // Decode post-index vector load/store lane instructions. 1442 // Decode post-index of load duplicate lane 1474 // Decode post-index of load/store lane 1516 // Decode lane 1519 unsigned lane = 0; local 1521 // NumLanes = 16 bytes / bytes of each lane 1524 case 16: // A vector has 16 lanes, each lane is 1 bytes. 1525 lane = (Q << 3) | S; 1528 lane [all...] |
/freebsd-10-stable/sys/dev/mlx5/mlx5_core/ |
H A D | mlx5_port.c | 628 int lane = 0; local 640 lane = MLX5_GET(pmlp_reg, out, lane0_module_mapping); 641 *module_num = lane & MLX5_EEPROM_IDENTIFIER_BYTE_MASK;
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/freebsd-10-stable/contrib/libpcap/ |
H A D | scanner.l | 289 lane return LANE;
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