Searched refs:Undef (Results 1 - 20 of 20) sorted by relevance

/freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h35 Undef = 0x20, enumerator in enum:llvm::RegState::__anon2021
39 DefineNoRead = Define | Undef,
73 flags & RegState::Undef,
396 return B ? RegState::Undef : 0;
/freebsd-10-stable/contrib/llvm/lib/Transforms/Scalar/
H A DStructurizeCFG.cpp526 Value *Undef = UndefValue::get(Phi.getType()); local
527 Phi.addIncoming(Undef, From);
549 Value *Undef = UndefValue::get(Phi->getType()); local
551 Updater.AddAvailableValue(&Func->getEntryBlock(), Undef);
552 Updater.AddAvailableValue(To, Undef);
564 Updater.AddAvailableValue(Dominator.getResult(), Undef);
859 Value *Undef = UndefValue::get(II->getType()); local
861 Updater.AddAvailableValue(&Func->getEntryBlock(), Undef);
H A DReassociate.cpp798 Constant *Undef = UndefValue::get(I->getType()); local
800 Undef, Undef, "", I);
/freebsd-10-stable/contrib/llvm/lib/Transforms/InstCombine/
H A DInstCombinePHI.cpp784 Value *Undef = UndefValue::get(FirstPhi.getType()); local
786 ReplaceInstUsesWith(*PHIsToSlice[i], Undef);
787 return ReplaceInstUsesWith(FirstPhi, Undef);
H A DInstCombineSimplifyDemanded.cpp856 return 0; // Undef.
944 Constant *Undef = UndefValue::get(EltTy); local
949 Elts.push_back(Undef);
958 Elts.push_back(Undef);
/freebsd-10-stable/contrib/llvm/include/llvm/IR/
H A DIRBuilder.h1438 Value *Undef = UndefValue::get(VectorType::get(V->getType(), NumElts)); local
1439 V = CreateInsertElement(Undef, V, ConstantInt::get(I32Ty, 0),
1444 return CreateShuffleVector(V, Undef, Zeros, Name + ".splat");
/freebsd-10-stable/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp4580 SDValue Undef = getUNDEF(Ptr.getValueType()); local
4581 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
4589 SDValue Undef = getUNDEF(Ptr.getValueType()); local
4590 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
4599 SDValue Undef = getUNDEF(Ptr.getValueType()); local
4600 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef,
4609 SDValue Undef = getUNDEF(Ptr.getValueType()); local
4610 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef,
4659 SDValue Undef = getUNDEF(Ptr.getValueType()); local
4660 SDValue Ops[] = { Chain, Val, Ptr, Undef };
4728 SDValue Undef = getUNDEF(Ptr.getValueType()); local
[all...]
H A DDAGCombiner.cpp2588 // Undef bits can contribute to a possible optimisation if set, so
5840 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
7491 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); local
7495 Undef.getNode()->dump(&DAG);
7498 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); local
/freebsd-10-stable/contrib/llvm/tools/clang/lib/CodeGen/
H A DCodeGenFunction.cpp545 llvm::Value *Undef = llvm::UndefValue::get(Int32Ty); local
546 AllocaInsertPt = new llvm::BitCastInst(Undef, Int32Ty, "", EntryBB);
H A DItaniumCXXABI.cpp1142 RValue Undef = RValue::get(llvm::UndefValue::get(T)); local
1143 return ItaniumCXXABI::EmitReturnFromThunk(CGF, Undef, ResultType);
/freebsd-10-stable/contrib/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp1645 Value *Undef = UndefValue::get(Ty); local
1646 Scalar->replaceAllUsesWith(Undef);
/freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp183 .addReg(DestReg, RegState::Undef)
/freebsd-10-stable/contrib/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp1909 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
3829 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4188 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4194 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
H A DX86ISelLowering.cpp5094 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
6246 // of the result come from the same quadword of one of the two inputs. Undef
8914 SDValue Undef = DAG.getUNDEF(InVT); local
8916 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8917 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
9045 SDValue Undef = DAG.getUNDEF(VT); local
9046 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
9047 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
9098 SDValue Undef = DAG.getUNDEF(MVT::v16i8); local
9099 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask
10448 SDValue Undef = DAG.getUNDEF(InVT); local
14455 unsigned Undef = MRI.createVirtualRegister(RC32); local
[all...]
H A DX86ISelDAGToDAG.cpp1844 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, local
1856 SDValue RetVals[] = { Undef, Ret };
/freebsd-10-stable/contrib/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1954 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); local
1964 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
1970 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
/freebsd-10-stable/contrib/llvm/lib/CodeGen/
H A DIfConversion.cpp992 MIB.addReg(Reg, RegState::Implicit | RegState::Undef);
/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp664 // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise
666 enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc; enumerator in enum:OpcTypes
/freebsd-10-stable/contrib/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp969 .addReg(ARM::CPSR, RegState::Undef);
H A DARMBaseInstrInfo.cpp4082 .addReg(DReg, RegState::Undef)

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