Searched refs:TT (Results 1 - 25 of 137) sorted by relevance

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/freebsd-10-stable/contrib/llvm/lib/Target/XCore/
H A DXCoreSubtarget.cpp26 XCoreSubtarget::XCoreSubtarget(const std::string &TT, argument
28 : XCoreGenSubtargetInfo(TT, CPU, FS)
/freebsd-10-stable/contrib/llvm/lib/Target/CppBackend/TargetInfo/
H A DCppBackendTargetInfo.cpp17 static unsigned CppBackend_TripleMatchQuality(const std::string &TT) { argument
/freebsd-10-stable/contrib/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCAsmInfo.cpp20 MSP430MCAsmInfo::MSP430MCAsmInfo(StringRef TT) { argument
H A DMSP430MCAsmInfo.h25 explicit MSP430MCAsmInfo(StringRef TT);
H A DMSP430MCTargetDesc.cpp40 static MCRegisterInfo *createMSP430MCRegisterInfo(StringRef TT) { argument
46 static MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU, argument
49 InitMSP430MCSubtargetInfo(X, TT, CPU, FS);
53 static MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
/freebsd-10-stable/contrib/llvm/lib/Target/MSP430/
H A DMSP430Subtarget.cpp26 MSP430Subtarget::MSP430Subtarget(const std::string &TT, argument
29 MSP430GenSubtargetInfo(TT, CPU, FS) {
H A DMSP430TargetMachine.cpp28 StringRef TT,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35 Subtarget(TT, CPU, FS),
27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DMSP430Subtarget.h33 MSP430Subtarget(const std::string &TT, const std::string &CPU,
/freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCAsmInfo.h24 explicit HexagonMCAsmInfo(StringRef TT);
H A DHexagonMCTargetDesc.cpp43 static MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT) { argument
49 static MCSubtargetInfo *createHexagonMCSubtargetInfo(StringRef TT, argument
53 InitHexagonMCSubtargetInfo(X, TT, CPU, FS);
58 StringRef TT) {
59 MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
69 static MCCodeGenInfo *createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
57 createHexagonMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) argument
H A DHexagonMCAsmInfo.cpp21 HexagonMCAsmInfo::HexagonMCAsmInfo(StringRef TT) { argument
/freebsd-10-stable/contrib/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCAsmInfo.h25 explicit MipsMCAsmInfo(StringRef TT);
H A DMipsMCAsmInfo.cpp21 MipsMCAsmInfo::MipsMCAsmInfo(StringRef TT) { argument
22 Triple TheTriple(TT);
/freebsd-10-stable/contrib/llvm/lib/Target/NVPTX/MCTargetDesc/
H A DNVPTXMCAsmInfo.h26 explicit NVPTXMCAsmInfo(const StringRef &TT);
H A DNVPTXMCAsmInfo.cpp28 NVPTXMCAsmInfo::NVPTXMCAsmInfo(const StringRef &TT) { argument
29 Triple TheTriple(TT);
/freebsd-10-stable/contrib/llvm/lib/Target/R600/MCTargetDesc/
H A DAMDGPUMCAsmInfo.h24 explicit AMDGPUMCAsmInfo(StringRef &TT);
/freebsd-10-stable/contrib/llvm/lib/Target/XCore/MCTargetDesc/
H A DXCoreMCAsmInfo.h26 explicit XCoreMCAsmInfo(StringRef TT);
H A DXCoreMCTargetDesc.cpp41 static MCRegisterInfo *createXCoreMCRegisterInfo(StringRef TT) { argument
47 static MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, argument
50 InitXCoreMCSubtargetInfo(X, TT, CPU, FS);
55 StringRef TT) {
56 MCAsmInfo *MAI = new XCoreMCAsmInfo(TT);
65 static MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
54 createXCoreMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) argument
/freebsd-10-stable/contrib/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp83 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) { argument
84 Triple triple(TT);
88 unsigned Len = TT.size();
93 if (Len >= 5 && TT.substr(0, 4) == "armv")
95 else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
97 if (Len >= 7 && TT[5] == 'v')
104 unsigned SubVer = TT[Idx];
114 if (Len >= Idx+2 && TT[Idx+1] == 'm') {
122 } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Id
188 createARMMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) argument
215 createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) argument
224 createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
238 createMCStreamer(const Target &T, StringRef TT, MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, bool RelaxAll, bool NoExecStack) argument
268 createARMMCRelocationInfo(StringRef TT, MCContext &Ctx) argument
[all...]
/freebsd-10-stable/contrib/llvm/lib/Target/Sparc/
H A DSparcTargetMachine.cpp28 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, argument
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35 Subtarget(TT, CPU, FS, is64bit),
86 StringRef TT, StringRef CPU,
92 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
98 StringRef TT, StringRef CPU,
104 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
85 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
97 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DSparcSubtarget.cpp27 SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU, argument
29 SparcGenSubtargetInfo(TT, CPU, FS),
/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/
H A DAArch64Subtarget.cpp31 AArch64Subtarget::AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS) argument
32 : AArch64GenSubtargetInfo(TT, CPU, FS), HasFPARMv8(false), HasNEON(false),
33 HasCrypto(false), TargetTriple(TT), CPUString(CPU) {
/freebsd-10-stable/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXSubtarget.cpp26 NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU, argument
28 : NVPTXGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), PTXVersion(0),
31 Triple T(TT);
/freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/
H A DSystemZSubtarget.cpp24 SystemZSubtarget::SystemZSubtarget(const std::string &TT, argument
27 : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
29 TargetTriple(TT) {
/freebsd-10-stable/contrib/llvm/lib/Target/CppBackend/
H A DCPPTargetMachine.h25 CPPTargetMachine(const Target &T, StringRef TT, argument
29 : TargetMachine(T, TT, CPU, FS, Options) {}

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