Searched refs:SuperReg (Results 1 - 7 of 7) sorted by relevance
/freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.cpp | 215 unsigned SuperReg = *SRI; local 218 return SuperReg; 247 unsigned SuperReg = uniqueSuperReg(Reg, TRI); local 253 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg); 254 CanUseDblStore = (SuperRegNext == SuperReg); 259 TII.storeRegToStackSlot(MBB, MI, SuperReg, true, 261 MBB.addLiveIn(SuperReg); 302 unsigned SuperReg = uniqueSuperReg(Reg, TRI); local 307 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg); 308 CanUseDblLoad = (SuperRegNext == SuperReg); [all...] |
/freebsd-10-stable/contrib/llvm/lib/CodeGen/ |
H A D | AggressiveAntiDepBreaker.cpp | 549 unsigned SuperReg = 0; 552 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg)) 553 SuperReg = Reg; 569 // All group registers should be a subreg of SuperReg. 572 if (Reg == SuperReg) continue; 573 bool IsSub = TRI->isSubRegister(SuperReg, Reg); 586 dbgs() << "*** Performing rename " << TRI->getName(SuperReg) << 591 // Check each possible rename register for SuperReg in round-robin 600 TRI->getMinimalPhysRegClass(SuperReg, MV [all...] |
H A D | PostRASchedulerList.cpp | 464 const unsigned SuperReg = MO.getReg(); local 466 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) {
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/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 728 SDValue SuperReg = SDValue(VLd, 0); 733 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); 824 SDValue SuperReg; local 854 SuperReg = SDValue(VLdDup, 0); 859 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); 930 SDValue SuperReg = createQTuple(Regs); local 932 Ops.push_back(SuperReg); // Source Reg 945 SuperReg = SDValue(VLdLn, 0); 949 SDValue SUB0 = CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg);
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/freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 1897 SDValue SuperReg = SDValue(VLd, 0); 1903 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); 2130 SDValue SuperReg; local 2135 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); 2137 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0); 2144 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); 2146 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); 2148 Ops.push_back(SuperReg); 2162 SuperReg = SDValue(VLdLn, 0); 2168 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); 2217 SDValue SuperReg; local [all...] |
/freebsd-10-stable/contrib/llvm/lib/Target/R600/ |
H A D | R600InstrInfo.cpp | 1079 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index); 1080 Reserved.set(SuperReg);
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H A D | SIISelLowering.cpp | 348 unsigned SuperReg = MI->getOperand(0).getReg(); local 364 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
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