Searched refs:RegList (Results 1 - 11 of 11) sorted by relevance
/freebsd-10-stable/contrib/llvm/utils/TableGen/ |
H A D | CallingConvEmitter.cpp | 110 ListInit *RegList = Action->getValueAsListInit("RegList"); local 111 if (RegList->getSize() == 1) { 113 O << getQualifiedName(RegList->getElementAsRecord(0)) << ")) {\n"; 115 O << IndentStr << "static const uint16_t RegList" << ++Counter 118 for (unsigned i = 0, e = RegList->getSize(); i != e; ++i) { 120 O << getQualifiedName(RegList->getElementAsRecord(i)); 123 O << IndentStr << "if (unsigned Reg = State.AllocateReg(RegList" 124 << Counter << ", " << RegList->getSize() << ")) {\n"; 131 ListInit *RegList local [all...] |
/freebsd-10-stable/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMELFStreamer.cpp | 79 virtual void emitRegSave(const SmallVectorImpl<unsigned> &RegList, 115 void ARMTargetAsmStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, 117 assert(RegList.size() && "RegList should not be empty"); 123 InstPrinter.printRegName(OS, RegList[0]); 125 for (unsigned i = 1, e = RegList.size(); i != e; ++i) { 127 InstPrinter.printRegName(OS, RegList[i]); 247 virtual void emitRegSave(const SmallVectorImpl<unsigned> &RegList, 301 void emitRegSave(const SmallVectorImpl<unsigned> &RegList, bool isVector); 469 void ARMTargetELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, [all...] |
/freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
H A D | ARMCallingConv.h | 31 static const uint16_t RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; local 34 if (unsigned Reg = State.AllocateReg(RegList, 4)) 49 if (unsigned Reg = State.AllocateReg(RegList, 4))
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H A D | ARMBaseRegisterInfo.cpp | 54 const uint16_t *RegList = (STI.isTargetIOS() && !STI.isAAPCS_ABI()) local 58 if (!MF) return RegList; 81 return RegList;
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H A D | ARMAsmPrinter.cpp | 997 SmallVector<unsigned, 4> RegList; local 1022 RegList.push_back(MO.getReg()); 1030 RegList.push_back(SrcReg); 1033 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
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H A D | ARMBaseInstrInfo.cpp | 1910 SmallVector<MachineOperand, 4> RegList; local 1912 RegList.push_back(MI->getOperand(i)); 1925 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false, 1947 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false, 1963 for (int i = RegList.size() - 1; i >= 0; --i) 1964 MIB.addOperand(RegList[i]);
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/freebsd-10-stable/contrib/llvm/include/llvm/MC/ |
H A D | MCStreamer.h | 89 virtual void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
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/freebsd-10-stable/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 287 static const uint16_t RegList[] = { local 290 static const unsigned NbRegs = array_lengthof(RegList); 332 unsigned Reg = State.AllocateReg(RegList, NbRegs);
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/freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 185 static const uint16_t RegList[] = { local 189 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
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/freebsd-10-stable/contrib/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 1609 const SmallVectorImpl<unsigned> &RegList = getRegList(); local 1611 I = RegList.begin(), E = RegList.end(); I != E; ++I) 2359 assert (Regs.size() > 0 && "RegList contains no registers?"); 2596 const SmallVectorImpl<unsigned> &RegList = getRegList(); local 2598 I = RegList.begin(), E = RegList.end(); I != E; ) {
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/freebsd-10-stable/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 56 static const uint16_t RegList[] = { local 60 if (unsigned Reg = State.AllocateReg(RegList, 6)) { 71 if (unsigned Reg = State.AllocateReg(RegList, 6))
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