/freebsd-10-stable/contrib/llvm/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 231 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) { argument 232 OutMI.setOpcode(NewOpc); 415 unsigned NewOpc; local 418 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; 419 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; 420 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; 421 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; 422 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; 423 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; 424 case X86::VMOVDQUrr: NewOpc 439 unsigned NewOpc; local [all...] |
H A D | X86InstrInfo.cpp | 3613 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate; 3664 unsigned NewOpc; local 3666 NewOpc = GetCondBranchFromCond(NewCC); 3668 NewOpc = getSETFromCond(NewCC, HasMemoryOperand); 3671 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(), 3678 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc)); 4288 unsigned NewOpc = 0; local 4292 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; 4293 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; 4294 case X86::TEST32rr: NewOpc 4356 unsigned NewOpc = 0; local 4605 unsigned NewOpc; local [all...] |
/freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
H A D | Thumb2InstrInfo.cpp | 489 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; 490 MI.setDesc(TII.get(NewOpc)); 523 unsigned NewOpc = Opcode; 533 NewOpc = immediateOffsetOpcode(Opcode); 545 NewOpc = negativeOffsetOpcode(Opcode); 550 NewOpc = positiveOffsetOpcode(Opcode); 580 if (NewOpc != Opcode) 581 MI.setDesc(TII.get(NewOpc)); 614 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
|
H A D | ARMLoadStoreOptimizer.cpp | 856 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); local 857 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) 955 unsigned NewOpc = 0; local 973 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, AddSub); 992 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, AddSub); 1010 BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) 1019 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { 1021 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) 1026 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), M 1152 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument 1215 unsigned NewOpc = (isLd) local 1238 unsigned NewOpc = (isLd) local 1501 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET); local 1655 CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, unsigned &EvenReg, unsigned &OddReg, unsigned &BaseReg, int &Offset, unsigned &PredReg, ARMCC::CondCodes &Pred, bool &isT2) argument 1824 unsigned NewOpc = 0; local [all...] |
H A D | ARMConstantIslandPass.cpp | 1701 unsigned NewOpc = 0; local 1708 NewOpc = ARM::tLEApcrel; 1715 NewOpc = ARM::tLDRpci; 1722 if (!NewOpc) 1735 U.MI->setDesc(TII->get(NewOpc)); 1755 unsigned NewOpc = 0; local 1761 NewOpc = ARM::tB; 1766 NewOpc = ARM::tBcc; 1772 if (NewOpc) { 1777 Br.MI->setDesc(TII->get(NewOpc)); [all...] |
H A D | ARMExpandPseudoInsts.cpp | 744 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; local 745 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), 783 unsigned NewOpc; local 785 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; 786 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; 787 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; 788 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; 791 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), 975 unsigned NewOpc = ARM::VLDMDIA; local 977 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 1006 unsigned NewOpc = ARM::VSTMDIA; local 1037 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q : local [all...] |
H A D | ARMISelLowering.cpp | 2670 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) local 2672 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(), 5702 unsigned NewOpc = 0; local 5707 NewOpc = ARMISD::VMULLs; 5712 NewOpc = ARMISD::VMULLu; 5717 NewOpc = ARMISD::VMULLs; 5720 NewOpc = ARMISD::VMULLu; 5724 NewOpc = ARMISD::VMULLu; 5729 if (!NewOpc) { 5748 return DAG.getNode(NewOpc, D 7636 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ? local 7660 unsigned NewOpc; local 8006 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode()); local 9354 unsigned NewOpc = 0; local 9473 unsigned NewOpc = 0; local [all...] |
H A D | Thumb1RegisterInfo.cpp | 462 unsigned NewOpc = convertToNonSPOpcode(Opcode); variable 463 if (NewOpc != Opcode && FrameReg != ARM::SP) 464 MI.setDesc(TII.get(NewOpc));
|
H A D | ARMISelDAGToDAG.cpp | 3036 unsigned NewOpc = isThumb ? ARM::t2LDREXD :ARM::LDREXD; local 3053 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops); 3114 unsigned NewOpc = isThumb ? ARM::t2STREXD : ARM::STREXD; local 3116 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
|
/freebsd-10-stable/contrib/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.h | 91 unsigned NewOpc) const;
|
H A D | MipsInstrInfo.h | 118 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
|
H A D | MipsSEISelLowering.h | 70 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
|
H A D | MipsInstrInfo.cpp | 285 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, argument 288 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
|
H A D | MipsLongBranch.cpp | 222 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); local 223 const MCInstrDesc &NewDesc = TII->get(NewOpc);
|
H A D | MipsSEInstrInfo.cpp | 440 unsigned NewOpc) const { 441 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
|
H A D | MipsSEISelLowering.cpp | 1154 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc, argument 1159 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
|
/freebsd-10-stable/contrib/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 2349 unsigned NewOpc; local 2352 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; 2353 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; 2354 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; 2355 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; 2356 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; 2357 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; 2358 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; 2359 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; 2360 case X86::VMOVUPDrr: NewOpc 2373 unsigned NewOpc; local [all...] |
/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 3603 unsigned NewOpc = 0; local 3609 case Intrinsic::arm_neon_vld1: NewOpc = AArch64ISD::NEON_LD1_UPD; 3611 case Intrinsic::arm_neon_vld2: NewOpc = AArch64ISD::NEON_LD2_UPD; 3613 case Intrinsic::arm_neon_vld3: NewOpc = AArch64ISD::NEON_LD3_UPD; 3615 case Intrinsic::arm_neon_vld4: NewOpc = AArch64ISD::NEON_LD4_UPD; 3617 case Intrinsic::arm_neon_vst1: NewOpc = AArch64ISD::NEON_ST1_UPD; 3619 case Intrinsic::arm_neon_vst2: NewOpc = AArch64ISD::NEON_ST2_UPD; 3621 case Intrinsic::arm_neon_vst3: NewOpc = AArch64ISD::NEON_ST3_UPD; 3623 case Intrinsic::arm_neon_vst4: NewOpc = AArch64ISD::NEON_ST4_UPD; 3625 case Intrinsic::aarch64_neon_vld1x2: NewOpc 3730 unsigned NewOpc = 0; local [all...] |
/freebsd-10-stable/contrib/llvm/lib/Target/R600/ |
H A D | SIInstrInfo.cpp | 175 int NewOpc; local 178 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1) 179 return NewOpc; 182 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1) 183 return NewOpc;
|
/freebsd-10-stable/contrib/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 6963 unsigned NewOpc; local 6966 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; 6967 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; 6968 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; 6972 TmpInst.setOpcode(NewOpc); 7437 unsigned NewOpc; local 7440 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 7441 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 7442 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 7443 case ARM::t2UXTB: NewOpc 7551 unsigned NewOpc; local 7590 unsigned NewOpc; local [all...] |
/freebsd-10-stable/contrib/llvm/lib/CodeGen/ |
H A D | MachineLICM.cpp | 1255 unsigned NewOpc = local 1260 if (NewOpc == 0) return 0; 1261 const MCInstrDesc &MID = TII->get(NewOpc);
|
H A D | TwoAddressInstructionPass.cpp | 1186 unsigned NewOpc = local 1191 if (NewOpc != 0) { 1192 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
|
/freebsd-10-stable/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 353 unsigned NewOpc = N->getOpcode(); local 363 NewOpc = ISD::FP_TO_SINT; 365 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
|