Searched refs:INT_MASK (Results 1 - 6 of 6) sorted by relevance

/freebsd-10-stable/sys/mips/adm5120/
H A Dif_admsw.c343 REG_WRITE(ADMSW_INT_MASK, INT_MASK);
344 REG_WRITE(ADMSW_INT_ST, INT_MASK);
1097 REG_WRITE(ADMSW_INT_ST, INT_MASK);
1145 REG_WRITE(ADMSW_INT_ST, INT_MASK);
1148 REG_WRITE(ADMSW_INT_MASK, INT_MASK);
H A Dif_admswreg.h192 #define INT_MASK 0x1FDEFFF macro
/freebsd-10-stable/sys/dev/drm2/radeon/
H A Dsi.c3316 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3317 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3319 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3320 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3323 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3324 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3544 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
3545 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
3547 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
3548 WREG32(INT_MASK
[all...]
H A Devergreen.c2598 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2599 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2601 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2602 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2605 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2606 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2807 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2808 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2810 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2811 WREG32(INT_MASK
[all...]
H A Dsid.h300 #define INT_MASK 0x6b40 macro
H A Devergreend.h831 #define INT_MASK 0x6b40 macro

Completed in 234 milliseconds