/freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/ |
H A D | RegisterScavenging.h | 20 #include "llvm/ADT/BitVector.h" 63 BitVector CalleeSavedRegs; 68 BitVector RegsAvailable; 72 BitVector KillRegs, DefRegs; 117 void getRegsUsed(BitVector &used, bool includeReserved); 121 BitVector getRegsAvailable(const TargetRegisterClass *RC); 180 void setUsed(BitVector &Regs) { 183 void setUnused(BitVector &Regs) { 192 void addRegWithSubRegs(BitVector &BV, unsigned Reg); 200 BitVector [all...] |
H A D | LiveRegMatrix.h | 27 #include "llvm/ADT/BitVector.h" 59 BitVector RegMaskUsable;
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H A D | RegisterClassInfo.h | 21 #include "llvm/ADT/BitVector.h" 63 BitVector Reserved;
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/freebsd-10-stable/contrib/llvm/tools/clang/include/clang/Analysis/Analyses/ |
H A D | ReachableCode.h | 24 class BitVector; 50 llvm::BitVector &Reachable);
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H A D | CFGReachabilityAnalysis.h | 19 #include "llvm/ADT/BitVector.h" 33 typedef llvm::BitVector ReachableSet;
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/freebsd-10-stable/contrib/llvm/include/llvm/ADT/ |
H A D | BitVector.h | 1 //===- llvm/ADT/BitVector.h - Bit vectors -----------------------*- C++ -*-===// 10 // This file implements the BitVector class. 27 class BitVector { class in namespace:llvm 39 friend class BitVector; 47 reference(BitVector &b, unsigned Idx) { 73 /// BitVector default ctor - Creates an empty bitvector. 74 BitVector() : Size(0), Capacity(0) { function in class:llvm::BitVector 78 /// BitVector ctor - Creates a bitvector of specified number of bits. All 80 explicit BitVector(unsigned s, bool t = false) : Size(s) { function in class:llvm::BitVector 88 /// BitVector cop 89 BitVector(const BitVector &RHS) : Size(RHS.size()) { function in class:llvm::BitVector 102 BitVector(BitVector &&RHS) function in class:llvm::BitVector [all...] |
H A D | SmallBitVector.h | 17 #include "llvm/ADT/BitVector.h" 32 // TODO: In "large" mode, a pointer to a BitVector is used, leading to an 88 BitVector *getPointer() const { 90 return reinterpret_cast<BitVector *>(X); 99 void switchToLarge(BitVector *BV) { 145 switchToLarge(new BitVector(s, t)); 153 switchToLarge(new BitVector(*RHS.getPointer())); 261 BitVector *BV = new BitVector(N, t); 274 BitVector *B [all...] |
/freebsd-10-stable/contrib/llvm/lib/Target/R600/ |
H A D | AMDGPURegisterInfo.h | 19 #include "llvm/ADT/BitVector.h" 37 virtual BitVector getReservedRegs(const MachineFunction &MF) const { 38 assert(!"Unimplemented"); return BitVector();
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H A D | R600RegisterInfo.h | 31 virtual BitVector getReservedRegs(const MachineFunction &MF) const;
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H A D | SIRegisterInfo.h | 30 virtual BitVector getReservedRegs(const MachineFunction &MF) const;
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H A D | R600RegisterInfo.cpp | 28 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const { 29 BitVector Reserved(getNumRegs());
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H A D | SIRegisterInfo.cpp | 27 BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 28 BitVector Reserved(getNumRegs());
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/freebsd-10-stable/contrib/llvm/lib/CodeGen/ |
H A D | SpillPlacement.h | 37 class BitVector; 51 BitVector *ActiveNodes; 98 void prepare(BitVector &RegBundles);
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H A D | CriticalAntiDepBreaker.h | 20 #include "llvm/ADT/BitVector.h" 44 const BitVector AllocatableSet; 68 BitVector KeepRegs;
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H A D | AggressiveAntiDepBreaker.h | 21 #include "llvm/ADT/BitVector.h" 126 BitVector CriticalPathSet; 177 BitVector GetRenameRegisters(unsigned Reg);
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H A D | RegisterScavenging.cpp | 65 BitVector PR = MBB->getParent()->getFrameInfo()->getPristineRegs(MBB); 106 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) { 249 void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) { 271 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) { 272 BitVector Mask(TRI->getNumRegs()); 287 BitVector &Candidates, 365 BitVector Candidates = 380 BitVector Available = getRegsAvailable(RC);
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H A D | TargetRegisterInfo.cpp | 15 #include "llvm/ADT/BitVector.h" 131 const TargetRegisterClass *RC, BitVector &R){ 138 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, 140 BitVector Allocatable(getNumRegs()); 154 BitVector Reserved = getReservedRegs(MF);
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/freebsd-10-stable/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430RegisterInfo.h | 40 BitVector getReservedRegs(const MachineFunction &MF) const;
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/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64RegisterInfo.h | 35 BitVector getReservedRegs(const MachineFunction &MF) const;
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/freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonRegisterInfo.h | 56 BitVector getReservedRegs(const MachineFunction &MF) const;
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/freebsd-10-stable/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcRegisterInfo.h | 39 BitVector getReservedRegs(const MachineFunction &MF) const;
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/freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.h | 57 virtual BitVector getReservedRegs(const MachineFunction &MF)
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/freebsd-10-stable/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.h | 47 BitVector getReservedRegs(const MachineFunction &MF) const;
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/freebsd-10-stable/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXRegisterInfo.cpp | 19 #include "llvm/ADT/BitVector.h" 94 BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 95 BitVector Reserved(getNumRegs());
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/freebsd-10-stable/contrib/llvm/lib/Target/Mips/ |
H A D | MipsRegisterInfo.h | 54 BitVector getReservedRegs(const MachineFunction &MF) const;
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