Searched refs:CACHE_LINE_SIZE (Results 1 - 10 of 10) sorted by relevance

/barrelfish-master/include/sys/
H A D_mutex.h62 } __aligned(CACHE_LINE_SIZE);
/barrelfish-master/include/arch/x86/barrelfish_kpi/
H A Dasm_inlines_arch.h86 uint8_t *line = (uint8_t *)((uintptr_t)base & ~(CACHE_LINE_SIZE-1UL));
89 line += CACHE_LINE_SIZE;
/barrelfish-master/include/arch/k1om/barrelfish_kpi/
H A Dasm_inlines_arch.h188 uint8_t *line = (uint8_t *)((uintptr_t)base & ~(CACHE_LINE_SIZE-1UL));
191 line += CACHE_LINE_SIZE;
/barrelfish-master/include/arch/x86_64/machine/
H A Dparam.h89 * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
93 #ifndef CACHE_LINE_SIZE
94 #define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT) macro
/barrelfish-master/include/arch/aarch64/machine/
H A Dparam.h77 * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
81 #define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT) macro
/barrelfish-master/include/arch/arm/machine/
H A Dparam.h105 * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
109 #define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT) macro
/barrelfish-master/include/vm/
H A Duma_int.h154 #define UMA_ALIGN __aligned(CACHE_LINE_SIZE)
H A Dvm_page.h220 } __aligned(CACHE_LINE_SIZE);
/barrelfish-master/usr/bench/mem_latency/
H A Dmemlatency.c271 assert(sizeof(struct elem) == CACHE_LINE_SIZE);
/barrelfish-master/usr/drivers/xeon_phi/
H A Dsysmem_caps.c286 assert(sizeof(struct elem) == CACHE_LINE_SIZE);

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