Searched refs:instruction (Results 1 - 23 of 23) sorted by relevance

/barrelfish-2018-10-04/usr/eclipseclp/Kernel/src/
H A Dsch_util.c81 int instruction = 0; local
106 instruction |= SCHSET_MAX2PUBLISH;
107 instruction |= SCHSET_MAXVALUE & tmp->val.nint;
114 instruction |= SCHSET_ROOT2BOTTOM;
116 instruction |= SCHSET_BOTTOM2ROOT;
118 instruction |= SCHSET_LEFT2RIGHT;
120 instruction |= SCHSET_RIGHT2LEFT;
122 instruction |= SCHSET_RESETCOUNTS;
124 instruction |= SCHSET_IDLING;
126 instruction |
579 int i, instruction = * (int *) infoval; local
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/barrelfish-2018-10-04/tools/fastmodels/
H A Dcache.c29 write_csselr_el1(int level, int instruction) { argument
32 * RES0 | level | instruction
34 uint64_t x= (instruction & 0x1) | ((level & 0x7) << 1);
65 /* Invalidate all instruction caches to point of unification. */
/barrelfish-2018-10-04/usr/eclipseclp/documents/internal/kernel/
H A Dkernel.tex328 \index{put instruction}
329 \index{get instruction}
340 located on the shared heap. The instruction just loads a pointer
413 \item[PP] program (code) pointer, points to next abstract machine instruction.
580 \index{get instruction}
594 \index{get instruction}
627 \index{get instruction}
648 \index{read instruction}
677 preceding get/write/read_structure/list instruction has constructed the
680 \index{write instruction}
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H A Ddebugger.tex254 Debug_call instruction:
257 Call instruction:
286 retry/trust instruction:
319 is caught by Restore_bp instruction, which does not contain the checks
321 instruction before (or after) the Restore_bp:
H A Druntime.tex405 get_constant/put_constant instruction. This means that all instances
/barrelfish-2018-10-04/usr/eclipseclp/Shm/src/
H A Dlock.S50 * Some SPARC implementations don't have the swap instruction
149 ; LDCWS instruction requires 16-byte alignment
/barrelfish-2018-10-04/usr/eclipseclp/Kernel/lib/
H A Dasm.pl57 % A single instruction is a term whose functor specifies the instruction
58 % and whose arguments are the instruction operands, e.g.
90 % <try refs> switches for try_parallel instruction
138 desc:html(" Assembles the WAM instruction WAMCode into the current ECLiPSe session
140 each element representing one WAM instruction. The format of the WAMCode
164 desc:html(" Assembles the WAM instruction WAMCode into the current ECLiPSe session
167 instruction. The format of the WAMCode is the same as that generated by
196 representing one WAM instruction. The format of the WAMCode is the same
235 element representing one WAM instruction
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H A Dstat.pl32 % If SEPIA is compiled with the PRINTAM option, virtual instruction
57 % pretty-prints the instruction statistics.
68 % pretty-prints the instruction pair statistics.
161 writeln('SEPIA abstract machine instruction statistics'),
304 writeln('SEPIA abstract machine instruction pair statistics'),
377 writeln('SEPIA abstract machine instruction pair counter'),
H A Dtracer_tty.pl481 trace_mode(13, []), % abstract instruction tracing on/off
H A Dfd.pl746 % A true which is not optimized away so that we have a call instruction which
/barrelfish-2018-10-04/lib/openssl-1.0.0d/crypto/
H A Dsparccpuid.S41 ! Following is V9 "rd %ccr,%o0" instruction. However! V8
245 ! Probe and instrument VIS1 instruction. Output is number of cycles it
/barrelfish-2018-10-04/doc/022-armv8/
H A Dreport.tex88 ARMv8 discards some long-standing features of the ARM instruction set:
93 instruction-set changes, however challenging to the systems programmer, are
515 indicating the instruction set to be used (much as is already done with
842 user-level execution address. In ARMv8, the \texttt{eret} instruction
853 longer be the target of a load instruction, but can only be loaded via a
860 multiple) instruction, there is no way to load the program counter with an
878 indirect jumps (load to PC) back to the instruction set.
884 8--29 for ARMv8 corresponds to the single \texttt{ldmia} instruction on lines
885 9 for ARMv7 --- one instruction is now 18, on the thread-switch critical path!
889 monitor) instruction i
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/barrelfish-2018-10-04/lib/cxx/unwind/
H A DUnwindRegistersRestore.S336 @ . the pc (r15) and lr (r14) cannot both be in the list in an LDM instruction
358 @ So, generate the instruction using the corresponding coprocessor mnemonic.
H A DUnwindRegistersSave.S313 @ . the pc (r15) cannot be in the list in an STM instruction
/barrelfish-2018-10-04/lib/acpica/source/tools/examples/
H A Dextables.c422 WBINVD instruction is operational (V1) : 0
/barrelfish-2018-10-04/usr/eclipseclp/icparc_solvers/ilog/
H A Dfd_min_max.pl388 % A true which is not optimized away so that we have a call instruction which
/barrelfish-2018-10-04/lib/openssl-1.0.0d/crypto/bn/asm/
H A Dpa-risc2.s15 ; by Gerry Kane for information on the instruction set architecture.
H A Dpa-risc2W.s9 ; by Gerry Kane for information on the instruction set architecture.
/barrelfish-2018-10-04/doc/026-device-queues/
H A Ddevif.tex131 instruction reordering and other optimizations. Currently X86 and Sparc can be
136 of the buffer. TSO is still a very strict memory model and only allows limited instruction
/barrelfish-2018-10-04/usr/eclipseclp/documents/userman/
H A Dumsusing.tex504 will then wait for a further instruction: either a \notation{<CR>}
/barrelfish-2018-10-04/doc/003-hake/
H A DHake.tex193 later). This list has a single element, the instruction to built an
/barrelfish-2018-10-04/doc/017-arm/
H A DARM.tex667 In-Order and O3. The first two are simple one-cycle-per-instruction
/barrelfish-2018-10-04/lib/tommath/
H A Dtommath.tex2626 is required for the product. In x86 terms for example, this means using the MUL instruction.
4273 then a x86 multiplier could produce the 62-bit product and use the ``shrd'' instruction to perform a double-precision right shift. The proof

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