| /freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/builtins/arm/ |
| H A D | addsf3vfp.S | 21 vadd.f32 s0, s0, s1
25 vadd.f32 s14, s14, s15
|
| H A D | divsf3vfp.S | 21 vdiv.f32 s0, s0, s1
25 vdiv.f32 s13, s14, s15
|
| H A D | extendsfdf2vfp.S | 22 vcvt.f64.f32 d0, s0
25 vcvt.f64.f32 d7, s15 // convert single to double
|
| H A D | fixsfsivfp.S | 22 vcvt.s32.f32 s0, s0
26 vcvt.s32.f32 s15, s15 // convert single to 32-bit int into s15
|
| H A D | fixunssfsivfp.S | 23 vcvt.u32.f32 s0, s0
27 vcvt.u32.f32 s15, s15 // convert single to 32-bit unsigned into s15
|
| H A D | floatsisfvfp.S | 23 vcvt.f32.s32 s0, s0
26 vcvt.f32.s32 s15, s15 // convert 32-bit int in s15 to float in s15
|
| H A D | floatunssisfvfp.S | 23 vcvt.f32.u32 s0, s0
26 vcvt.f32.u32 s15, s15 // convert 32-bit int in s15 to float in s15
|
| H A D | mulsf3vfp.S | 21 vmul.f32 s0, s0, s1
25 vmul.f32 s13, s14, s15
|
| H A D | subsf3vfp.S | 22 vsub.f32 s0, s0, s1
26 vsub.f32 s14, s14, s15
|
| H A D | truncdfsf2vfp.S | 22 vcvt.f32.f64 s0, d0
25 vcvt.f32.f64 s15, d7 // convert double to single (trucate precision)
|
| H A D | negsf2vfp.S | 21 vneg.f32 s0, s0
|
| H A D | eqsf2vfp.S | 22 vcmp.f32 s0, s1
26 vcmp.f32 s14, s15
|
| H A D | gesf2vfp.S | 22 vcmp.f32 s0, s1
26 vcmp.f32 s14, s15
|
| H A D | gtsf2vfp.S | 22 vcmp.f32 s0, s1
26 vcmp.f32 s14, s15
|
| H A D | lesf2vfp.S | 22 vcmp.f32 s0, s1
26 vcmp.f32 s14, s15
|
| H A D | ltsf2vfp.S | 22 vcmp.f32 s0, s1
26 vcmp.f32 s14, s15
|
| H A D | nesf2vfp.S | 22 vcmp.f32 s0, s1
26 vcmp.f32 s14, s15
|
| H A D | unordsf2vfp.S | 22 vcmp.f32 s0, s1
26 vcmp.f32 s14, s15
|
| /freebsd-11-stable/lib/libc/arm/aeabi/ |
| H A D | aeabi_vfp_float.S | 39 vcmp.f32 s0, s1
47 vcmpe.f32 s0, s1
55 vcmpe.f32 s1, s0
63 vcmp.f32 s0, s1
74 vcmp.f32 s0, s1
85 vcmp.f32 s0, s1
96 vcmp.f32 s0, s1
107 vcmp.f32 s0, s1
118 vcmp.f32 s0, s1
135 vcvt.s32.f32 s
[all...] |
| /freebsd-11-stable/sys/sparc64/sparc64/ |
| H A D | support.S | 597 stda %f32, [PCB_REG + PCB_UFP + (2 * VIS_BLOCKSIZE)] %asi
614 fsrc1 %f0, %f32
622 stda %f32, [%o1] %asi
628 fsrc1 %f16, %f32
636 stda %f32, [%o1] %asi
670 stda %f32, [PCB_REG + PCB_UFP + (2 * VIS_BLOCKSIZE)] %asi
686 fmovd %f0, %f32
715 stda %f32, [%o1] %asi
717 fmovd %f0, %f32
740 stda %f32, [
[all...] |
| /freebsd-11-stable/crypto/openssl/crypto/bn/asm/ |
| H A D | ia64.S | 135 // (f32-f128) FP register bank over process context switch, thus
141 // programs for that matter) with -mfixed-range=f32-f127 command
332 { .mfi; (p16) ldf8 f32=[r15],8
370 { .mfi; (p16) ldf8 f32=[r33],8
437 { .mfi; (p16) ldf8 f32=[r15],8 // *(ap++)
500 { .mfi; (p16) ldf8 f32=[r33],8
636 ldf8 f32=[r33],32 };;
658 xma.hu f41=f32,f120,f0 }
659 { .mfi; xma.lu f40=f32,f120,f0 };; // (*)
660 { .mfi; xma.hu f51=f32,f12
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 302 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
303 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 },
306 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
307 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 },
310 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 },
311 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 },
314 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 },
315 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 },
318 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 },
319 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 59 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass);
126 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
127 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
128 setCondCodeAction(ISD::SETLT, MVT::f32, Expand);
129 setCondCodeAction(ISD::SETLE, MVT::f32, Expand);
130 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
131 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
132 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
133 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
134 setCondCodeAction(ISD::SETUGE, MVT::f32, Expan
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| H A D | WebAssemblyMCTargetDesc.cpp | 139 case MVT::f32:
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 163 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
222 if (RetVT == MVT::f32)
224 } else if (OpVT == MVT::f32) {
248 if (OpVT == MVT::f32)
258 } else if (RetVT == MVT::f32) {
285 if (OpVT == MVT::f32) {
327 if (OpVT == MVT::f32) {
370 if (RetVT == MVT::f32)
381 if (RetVT == MVT::f32)
392 if (RetVT == MVT::f32)
[all...] |