Searched refs:cache (Results 1 - 25 of 63) sorted by relevance

123

/barrelfish-2018-10-04/lib/vfs/
H A Dvfs_cache.c111 free_unused(struct fs_cache *cache, size_t factor, size_t maximum) argument
118 unused_overburden = cache->unused_count;
120 else if (maximum > 0 && cache->unused_count > maximum) {
121 unused_overburden = cache->unused_count - maximum;
126 if (cache->unused_count > maximum) {
130 unused_overburden = cache->unused_count;
134 else if (cache->unused_count > cache->capacity / factor) {
135 unused_overburden = cache->unused_count - cache
185 cache_make_space(struct fs_cache *cache) argument
259 get_new_entry(struct fs_cache *cache, size_t hash, struct cache_entry **entry) argument
281 remove_from_unused(struct fs_cache *cache, struct cache_entry *entry) argument
307 fs_cache_acquire(struct fs_cache *cache, uint32_t key, void **item) argument
344 fs_cache_put(struct fs_cache *cache, uint32_t key, void *item) argument
408 fs_cache_release(struct fs_cache* cache, uint32_t key) argument
463 struct fs_cache *cache; local
491 fs_cache_free(struct fs_cache *cache) argument
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H A Dvfs_cache.h9 // Initialize cache.
12 errval_t fs_cache_init(size_t max_capacity, size_t map_size, struct fs_cache **cache);
14 // Free cache.
15 void fs_cache_free(struct fs_cache *cache);
17 // Acquire a reference to a cache entry. The reference must be released with
20 // - FS_CACHE_NOTPRESENT: There is no item with the given key in the cache.
21 errval_t fs_cache_acquire(struct fs_cache *cache, uint32_t key, void **item);
23 // Put an entry into the cache. The reference must be released with
31 errval_t fs_cache_put(struct fs_cache *cache, uint32_t key, void *item);
36 // - FS_CACHE_NOTPRESENT: There is no item with the given key in the cache
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/barrelfish-2018-10-04/lib/openssl-1.0.0d/crypto/x509v3/
H A Dpcy_cache.c69 /* Set cache entry according to CertificatePolicies extension.
78 X509_POLICY_CACHE *cache = x->policy_cache; local
83 cache->data = sk_X509_POLICY_DATA_new(policy_data_cmp);
84 if (!cache->data)
97 if (cache->anyPolicy)
102 cache->anyPolicy = data;
104 else if (sk_X509_POLICY_DATA_find(cache->data, data) != -1)
109 else if (!sk_X509_POLICY_DATA_push(cache->data, data))
122 sk_X509_POLICY_DATA_pop_free(cache->data, policy_data_free);
123 cache
131 X509_POLICY_CACHE *cache; local
235 policy_cache_free(X509_POLICY_CACHE *cache) argument
260 policy_cache_find_data(const X509_POLICY_CACHE *cache, const ASN1_OBJECT *id) argument
[all...]
H A Dpcy_map.c65 /* Set policy mapping entries in cache.
73 X509_POLICY_CACHE *cache = x->policy_cache; local
93 data = policy_cache_find_data(cache, map->issuerDomainPolicy);
95 if (!data && !cache->anyPolicy)
102 cache->anyPolicy->flags
106 data->qualifier_set = cache->anyPolicy->qualifier_set;
110 if (!sk_X509_POLICY_DATA_push(cache->data, data))
H A Dpcy_tree.c148 const X509_POLICY_CACHE *cache; local
182 /* First setup policy cache in all certificates apart from the
183 * trust anchor. Note any bad cache results on the way. Also can
190 cache = policy_cache_set(x);
191 /* If cache NULL something bad happened: return immediately */
192 if (cache == NULL)
200 else if ((ret == 1) && !cache->data)
206 if ((cache->explicit_skip != -1)
207 && (cache->explicit_skip < explicit_policy))
208 explicit_policy = cache
340 tree_link_nodes(X509_POLICY_LEVEL *curr, const X509_POLICY_CACHE *cache) argument
374 tree_add_unmatched(X509_POLICY_LEVEL *curr, const X509_POLICY_CACHE *cache, const ASN1_OBJECT *id, X509_POLICY_NODE *node, X509_POLICY_TREE *tree) argument
402 tree_link_unmatched(X509_POLICY_LEVEL *curr, const X509_POLICY_CACHE *cache, X509_POLICY_NODE *node, X509_POLICY_TREE *tree) argument
442 tree_link_any(X509_POLICY_LEVEL *curr, const X509_POLICY_CACHE *cache, X509_POLICY_TREE *tree) argument
700 const X509_POLICY_CACHE *cache; local
[all...]
H A Dpcy_int.h186 X509_POLICY_DATA *policy_cache_find_data(const X509_POLICY_CACHE *cache,
195 void policy_cache_free(X509_POLICY_CACHE *cache);
/barrelfish-2018-10-04/lib/devif/backends/net/mlx4/drivers/infiniband/core/
H A Dcache.c76 struct ib_gid_cache *cache;
83 read_lock_irqsave(&device->cache.lock, flags);
85 cache = device->cache.gid_cache[port_num - start_port(device)];
87 if (index < 0 || index >= cache->table_len)
90 *gid = cache->table[index];
92 read_unlock_irqrestore(&device->cache.lock, flags);
103 struct ib_gid_cache *cache;
112 read_lock_irqsave(&device->cache.lock, flags);
115 cache
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H A DMakefile11 device.o fmr_pool.o cache.o
/barrelfish-2018-10-04/tools/harness/tests/
H A Drpctests.py251 ''' UMP cache utilisation microbenchmark '''
281 for cache in ['Data', 'Instruction']:
282 data[cache] = []
283 index[cache] = None
284 iteration[cache] = 1
287 m = re.match("(Data|Instruction) cache miss\s+(\d+)\s+(\d+)\s+(\d+)",
290 cache = m.group(1)
293 if index[cache] is not None and i < index[cache]: # new iteration
294 results[cache]
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/barrelfish-2018-10-04/lib/openssl-1.0.0d/demos/tunala/
H A Dautoungunk.sh19 rm -rf autom4te.cache
/barrelfish-2018-10-04/usr/eclipseclp/Alog/src/
H A Dconfigure19 cache_file=./config.cache
85 -cache-file | --cache-file | --cache-fil | --cache-fi \
86 | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
88 -cache-file=* | --cache
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/barrelfish-2018-10-04/usr/eclipseclp/Usc/src/
H A Dconfigure19 cache_file=./config.cache
85 -cache-file | --cache-file | --cache-fil | --cache-fi \
86 | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
88 -cache-file=* | --cache
[all...]
/barrelfish-2018-10-04/kernel/include/arch/armv7/
H A Dcp15.h101 uint32_t cache; local
102 __asm volatile("mrc p15, 0, %[cache], c1, c0, 0" : [cache] "=r" (cache));
103 return cache;
H A Dpaging_kernel_arch.h20 #include <cache.h>
/barrelfish-2018-10-04/kernel/include/arch/armv8/
H A Dsysreg.h168 * C5.3 A64 system instructions for cache maintenance
259 uint64_t cache; local
260 __asm volatile(" mrs %[cache], sctlr_el1" : [cache] "=r" (cache));
261 return cache;
/barrelfish-2018-10-04/lib/devif/backends/net/mlx4/include/rdma/
H A Dib_fmr_pool.h52 * @cache:If set, FMRs may be reused after unmapping for identical map
64 unsigned cache:1; member in struct:ib_fmr_pool_param
/barrelfish-2018-10-04/usr/skb/programs/
H A Dthreadallocation.pl28 % single cache line
31 cache(_, CoreID, 1, data, _, _, LineSize, _),
53 cache(_, CH, 1, data, _, _, LineSize, _),
58 cache(_, CL, 1, data, _, _, LineSizeLast, _),
/barrelfish-2018-10-04/usr/eclipseclp/Pds/src/
H A Dconfigure19 cache_file=./config.cache
85 -cache-file | --cache-file | --cache-fil | --cache-fi \
86 | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
88 -cache-file=* | --cache
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/barrelfish-2018-10-04/include/vm/
H A Duma_core.c47 * - Investigate cache size adjustments
122 /* The boot-time adjusted value for cache line alignment. */
135 /* Linked list of all cache-only zones in the system */
672 uma_cache_t cache; local
688 cache = &zone->uz_cpu[cpu];
689 bucket_drain(zone, cache->uc_allocbucket);
690 bucket_drain(zone, cache->uc_freebucket);
691 if (cache->uc_allocbucket != NULL)
692 bucket_free(zone, cache->uc_allocbucket, NULL);
693 if (cache
717 uma_cache_t cache; local
2089 uma_cache_t cache; local
2630 uma_cache_t cache; local
3290 cache_print(uma_cache_t cache) argument
3324 uma_cache_t cache; local
3355 uma_cache_t cache; local
3409 uma_cache_t cache; local
[all...]
/barrelfish-2018-10-04/lib/libc/nls/
H A Dmsgcat.c89 SLIST_INSERT_HEAD(&cache, np, list); \
109 SLIST_HEAD(listhead, catentry) cache =
110 SLIST_HEAD_INITIALIZER(cache);
143 /* Try to get it from the cache first */
145 SLIST_FOREACH(np, &cache, list) {
336 SLIST_REMOVE(&cache, np, catentry, list);
354 /* Remove from cache if not referenced any more */
356 SLIST_FOREACH(np, &cache, list) {
384 * One more try in cache; if it was not found by name,
388 SLIST_FOREACH(np, &cache, lis
[all...]
/barrelfish-2018-10-04/lib/openssl-1.0.0d/crypto/des/times/
H A Dusparc.cc29 4 r2 i 63535.10 13.4% <-- very very weird, must be cache problems.
/barrelfish-2018-10-04/kernel/arch/arm/
H A Dexec.c17 #include <cache.h>
26 #include <cp15.h> // for invalidating tlb and cache
/barrelfish-2018-10-04/doc/015-disk-driver-arch/
H A Dfat.tex63 The FAT code uses a cache layer as a global block and cluster store,
64 simplifying the code and improving performance. The cache is implemented as a
67 unused cache entries that can be freed if space is required. Clients must
68 acquire a reference to a cache entry, either using \lstinline+fs_cache_acquire+
74 the cache is at its maximum capacity, it can pop the front entry from the
75 unused list, free its data, and use the entry for the new cache item.
79 \item \lstinline+fs_cache_init+ and \lstinline+fs_cache_free+, for cache
85 \item \lstinline+fs_cache_put+, for adding an item to the cache. This also
/barrelfish-2018-10-04/doc/009-notifications/
H A DNotify.tex44 work efficiently given the cache-coherence protocols of a typical NUMA
65 \subsection{Polling and cache coherence}
66 Sending a message involves the sender modifying a single cache line
68 cache line starts in shared (S) mode in the cache of both sender and
69 receiver cores. When the sender writes to the cache line this causes a
71 the receiver's cache. On most of our NUMA systems, be they
73 broadcast. Newer AMD Istanbul processors have a directory-based cache
75 pulls the modified cache line from the sender's cache resultin
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/barrelfish-2018-10-04/usr/eclipseclp/Shm/src/
H A DMakefile.in93 $(RM) config.cache config.log

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