Searched refs:_ENABLE_MASK (Results 1 - 8 of 8) sorted by relevance

/barrelfish-2018-10-04/lib/msun/aarch64/
H A Dfenv.h72 #define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT) macro
162 *__envp = __r & _ENABLE_MASK;
176 *__envp = __r & _ENABLE_MASK;
177 __r &= ~(_ENABLE_MASK);
182 __r &= ~(_ENABLE_MASK);
191 __msr_fpcr((*__envp) & _ENABLE_MASK);
239 return ((__r & _ENABLE_MASK) >> _FPUSW_SHIFT);
/barrelfish-2018-10-04/include/arch/aarch64/
H A Dfenv.h72 #define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT) macro
162 *__envp = __r & _ENABLE_MASK;
176 *__envp = __r & _ENABLE_MASK;
177 __r &= ~(_ENABLE_MASK);
182 __r &= ~(_ENABLE_MASK);
191 __msr_fpcr((*__envp) & _ENABLE_MASK);
239 return ((__r & _ENABLE_MASK) >> _FPUSW_SHIFT);
/barrelfish-2018-10-04/lib/msun/mips/
H A Dfenv.h65 #define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT) macro
160 __env &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
216 return ((__fpsr & _ENABLE_MASK) >> _FPUSW_SHIFT);
/barrelfish-2018-10-04/lib/msun/riscv/
H A Dfenv.h78 #define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT) macro
163 __env &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
221 return ((__fpsr & _ENABLE_MASK) >> _FPUSW_SHIFT);
/barrelfish-2018-10-04/lib/msun/powerpc/
H A Dfenv.h86 #define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ macro
209 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
250 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
263 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
272 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT);
/barrelfish-2018-10-04/lib/msun/sparc64/
H A Dfenv.h72 #define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT) macro
197 __r &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
253 return ((__r & _ENABLE_MASK) >> _FPUSW_SHIFT);
/barrelfish-2018-10-04/lib/msun/arm/
H A Dfenv.h84 #define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT) macro
/barrelfish-2018-10-04/include/arch/arm/
H A Dfenv.h84 #define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT) macro

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