Searched refs:wcreg (Results 1 - 4 of 4) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/sound/pci/
H A Drme32.c200 u32 wcreg; /* cached write control register value */ member in struct:rme32
238 #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
402 writel(rme32->wcreg | RME32_WCR_PD,
404 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
411 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
412 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
426 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
495 ds = rme32->wcreg & RME32_WCR_DS_BM;
498 rme32->wcreg &= ~RME32_WCR_DS_BM;
499 rme32->wcreg
[all...]
H A Drme96.c208 u32 wcreg; /* cached write control register value */ member in struct:rme96
243 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
244 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
503 writel(rme96->wcreg | RME96_WCR_PD,
505 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
511 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
512 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
520 rme96->wcreg |= RME96_WCR_MONITOR_0;
522 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
525 rme96->wcreg |
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/sound/pci/
H A Drme32.c200 u32 wcreg; /* cached write control register value */ member in struct:rme32
238 #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
402 writel(rme32->wcreg | RME32_WCR_PD,
404 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
411 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
412 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
426 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
495 ds = rme32->wcreg & RME32_WCR_DS_BM;
498 rme32->wcreg &= ~RME32_WCR_DS_BM;
499 rme32->wcreg
[all...]
H A Drme96.c208 u32 wcreg; /* cached write control register value */ member in struct:rme96
243 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
244 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
503 writel(rme96->wcreg | RME96_WCR_PD,
505 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
511 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
512 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
520 rme96->wcreg |= RME96_WCR_MONITOR_0;
522 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
525 rme96->wcreg |
[all...]

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