Searched refs:pllc1_clk (Results 1 - 6 of 6) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-shmobile/
H A Dclock-sh7367.c108 static struct clk pllc1_clk = { variable in typeref:struct:clk
117 .parent = &pllc1_clk,
147 &pllc1_clk,
180 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
272 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
H A Dclock-sh7377.c117 static struct clk pllc1_clk = { variable in typeref:struct:clk
126 .parent = &pllc1_clk,
157 &pllc1_clk,
190 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
281 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
H A Dclock-sh7372.c134 static struct clk pllc1_clk = { variable in typeref:struct:clk
144 .parent = &pllc1_clk,
305 &pllc1_clk,
339 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
459 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-shmobile/
H A Dclock-sh7367.c108 static struct clk pllc1_clk = { variable in typeref:struct:clk
117 .parent = &pllc1_clk,
147 &pllc1_clk,
180 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
272 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
H A Dclock-sh7377.c117 static struct clk pllc1_clk = { variable in typeref:struct:clk
126 .parent = &pllc1_clk,
157 &pllc1_clk,
190 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
281 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
H A Dclock-sh7372.c134 static struct clk pllc1_clk = { variable in typeref:struct:clk
144 .parent = &pllc1_clk,
305 &pllc1_clk,
339 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
459 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),

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