Searched refs:jz4740_timer_base (Results 1 - 4 of 4) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/jz4740/
H A Dtimer.c24 void __iomem *jz4740_timer_base; variable
28 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
34 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
40 jz4740_timer_base = ioremap(JZ4740_TCU_BASE_ADDR, 0x100);
42 if (!jz4740_timer_base)
46 writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
49 writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
H A Dtimer.h61 extern void __iomem *jz4740_timer_base;
66 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
71 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
76 return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
81 writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
86 writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
92 writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
97 writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
102 writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
107 return readw(jz4740_timer_base
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/jz4740/
H A Dtimer.c24 void __iomem *jz4740_timer_base; variable
28 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
34 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
40 jz4740_timer_base = ioremap(JZ4740_TCU_BASE_ADDR, 0x100);
42 if (!jz4740_timer_base)
46 writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
49 writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
H A Dtimer.h61 extern void __iomem *jz4740_timer_base;
66 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
71 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
76 return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
81 writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
86 writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
92 writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
97 writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
102 writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
107 return readw(jz4740_timer_base
[all...]

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