/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/plat-s3c24xx/ |
H A D | clock.c | 58 clk_f.rate = fclk;
|
H A D | clock-dclk.c | 136 else if (parent == &clk_f)
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-s3c24xx/ |
H A D | clock.c | 58 clk_f.rate = fclk;
|
H A D | clock-dclk.c | 136 else if (parent == &clk_f)
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s3c2440/ |
H A D | s3c244x-clock.c | 51 if (parent == &clk_f) 86 clk_arm.parent = (camdivn & S3C2440_CAMDIVN_DVSEN) ? &clk_h : &clk_f;
|
H A D | mach-rx1950.c | 516 s3c24xx_clkout1.parent = &clk_f;
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s3c2440/ |
H A D | s3c244x-clock.c | 51 if (parent == &clk_f) 86 clk_arm.parent = (camdivn & S3C2440_CAMDIVN_DVSEN) ? &clk_h : &clk_f;
|
H A D | mach-rx1950.c | 516 s3c24xx_clkout1.parent = &clk_f;
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/plat-samsung/include/plat/ |
H A D | clock.h | 64 extern struct clk clk_f;
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-samsung/include/plat/ |
H A D | clock.h | 64 extern struct clk clk_f;
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-ep93xx/ |
H A D | clock.c | 76 static struct clk clk_f = { variable in typeref:struct:clk 210 INIT_CK(NULL, "fclk", &clk_f), 529 clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; 557 clk_f.rate / 1000000, clk_h.rate / 1000000,
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s3c2410/ |
H A D | s3c2410.c | 120 .parent = &clk_f,
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s3c2410/ |
H A D | s3c2410.c | 120 .parent = &clk_f,
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-ep93xx/ |
H A D | clock.c | 76 static struct clk clk_f = { variable in typeref:struct:clk 210 INIT_CK(NULL, "fclk", &clk_f), 529 clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; 557 clk_f.rate / 1000000, clk_h.rate / 1000000,
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/plat-samsung/ |
H A D | clock.c | 294 struct clk clk_f = { variable in typeref:struct:clk 438 if (s3c24xx_register_clock(&clk_f) < 0)
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-samsung/ |
H A D | clock.c | 294 struct clk clk_f = { variable in typeref:struct:clk 438 if (s3c24xx_register_clock(&clk_f) < 0)
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s3c2412/ |
H A D | clock.c | 245 if (parent == &clk_msysclk || parent == &clk_f) 704 clk_f.parent = &clk_msysclk;
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s3c2412/ |
H A D | clock.c | 245 if (parent == &clk_msysclk || parent == &clk_f) 704 clk_f.parent = &clk_msysclk;
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5p6442/ |
H A D | clock.c | 330 clk_f.rate = arm;
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5p6442/ |
H A D | clock.c | 330 clk_f.rate = arm;
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pv310/ |
H A D | clock.c | 549 clk_f.rate = armclk;
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pv310/ |
H A D | clock.c | 549 clk_f.rate = armclk;
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s3c64xx/ |
H A D | clock.c | 791 clk_f.rate = fclk;
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5p6440/ |
H A D | clock.c | 804 clk_f.rate = fclk;
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s3c64xx/ |
H A D | clock.c | 791 clk_f.rate = fclk;
|