Searched refs:cfg_reg (Results 1 - 25 of 52) sorted by relevance

123

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/isdn/hisax/
H A Davm_a1p.c67 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_REG_OFFSET+offset);
68 ret = bytein(cs->hw.avm.cfg_reg+DATAREG_OFFSET);
76 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_REG_OFFSET+offset);
77 byteout(cs->hw.avm.cfg_reg+DATAREG_OFFSET, value);
83 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_FIFO_OFFSET);
84 insb(cs->hw.avm.cfg_reg+DATAREG_OFFSET, data, size);
90 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_FIFO_OFFSET);
91 outsb(cs->hw.avm.cfg_reg+DATAREG_OFFSET, data, size);
100 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,
102 ret = bytein(cs->hw.avm.cfg_reg
[all...]
H A Dteles3.c162 if (cs->hw.teles3.cfg_reg) {
164 release_region(cs->hw.teles3.cfg_reg, 1);
166 release_region(cs->hw.teles3.cfg_reg, 8);
179 if ((cs->hw.teles3.cfg_reg) && (cs->typ != ISDN_CTYPE_COMPAQ_ISA)) {
209 byteout(cs->hw.teles3.cfg_reg + 4, irqcfg);
211 byteout(cs->hw.teles3.cfg_reg + 4, irqcfg | 1);
214 byteout(cs->hw.teles3.cfg_reg, 0xff);
216 byteout(cs->hw.teles3.cfg_reg, 0x00);
331 cs->hw.teles3.cfg_reg = card->para[1];
332 switch (cs->hw.teles3.cfg_reg) {
[all...]
H A Ds0box.c98 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset));
104 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset, value);
110 read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size);
116 write_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size);
122 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset));
128 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset, value);
135 #define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg)
136 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg, data)
137 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscxfifo[nr], ptr, cnt)
138 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.teles3.cfg_reg, c
[all...]
H A Davm_a1.c110 while (((sval = bytein(cs->hw.avm.cfg_reg)) & 0xf) != 0x7) {
112 byteout(cs->hw.avm.cfg_reg, 0x1E);
113 sval = bytein(cs->hw.avm.cfg_reg);
140 release_region(cs->hw.avm.cfg_reg, 8);
169 byteout(cs->hw.avm.cfg_reg, 0x16);
170 byteout(cs->hw.avm.cfg_reg, 0x1E);
192 cs->hw.avm.cfg_reg = card->para[1] + 0x1800;
200 if (!request_region(cs->hw.avm.cfg_reg, 8, "avm cfg")) {
203 cs->hw.avm.cfg_reg,
204 cs->hw.avm.cfg_reg
[all...]
H A Dteles0.c187 if (cs->hw.teles0.cfg_reg)
188 release_region(cs->hw.teles0.cfg_reg, 8);
198 if (cs->hw.teles0.cfg_reg) {
229 byteout(cs->hw.teles0.cfg_reg + 4, cfval);
231 byteout(cs->hw.teles0.cfg_reg + 4, cfval | 1);
279 cs->hw.teles0.cfg_reg = card->para[2];
281 cs->hw.teles0.cfg_reg = 0;
290 if (cs->hw.teles0.cfg_reg) {
291 if (!request_region(cs->hw.teles0.cfg_reg, 8, "teles cfg")) {
295 cs->hw.teles0.cfg_reg,
[all...]
H A Dsportster.c129 bytein(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ +1);
139 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, 0);
141 adr = cs->hw.spt.cfg_reg + i *1024;
150 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq);
153 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq);
176 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq);
192 adr = cs->hw.spt.cfg_reg + i *1024;
204 adr = cs->hw.spt.cfg_reg + j *1024;
222 cs->hw.spt.cfg_reg = card->para[1];
226 cs->hw.spt.isac = cs->hw.spt.cfg_reg
[all...]
H A Dsedlbauer.c404 if (cs->hw.sedl.cfg_reg)
405 release_region(cs->hw.sedl.cfg_reg, bytecnt);
427 byteout(cs->hw.sedl.cfg_reg +3, cs->hw.sedl.reset_on);
429 byteout(cs->hw.sedl.cfg_reg +3, cs->hw.sedl.reset_off);
454 byteout(cs->hw.sedl.cfg_reg+ 5, 0);
474 byteout(cs->hw.sedl.cfg_reg+ 5, 0x02);
501 byteout(cs->hw.sedl.cfg_reg +3, cs->hw.sedl.reset_off);
512 byteout(cs->hw.sedl.cfg_reg +3, cs->hw.sedl.reset_off);
568 cs->hw.sedl.cfg_reg = card->para[1];
619 cs->hw.sedl.cfg_reg
[all...]
H A Davm_pci.c83 outb(idx, cs->hw.avm.cfg_reg + 4);
93 outb(idx, cs->hw.avm.cfg_reg + 4);
100 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4);
107 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4);
117 outl(idx, cs->hw.avm.cfg_reg + 4);
127 outl(idx, cs->hw.avm.cfg_reg + 4);
137 outb(idx, cs->hw.avm.cfg_reg + 4);
147 outb(idx, cs->hw.avm.cfg_reg + 4);
264 outl(idx, cs->hw.avm.cfg_reg + 4);
274 outb(idx, cs->hw.avm.cfg_reg
[all...]
H A Dmic.c163 if (cs->hw.mic.cfg_reg)
164 release_region(cs->hw.mic.cfg_reg, bytecnt);
203 cs->hw.mic.cfg_reg = card->para[1];
205 cs->hw.mic.adr = cs->hw.mic.cfg_reg + MIC_ADR;
206 cs->hw.mic.isac = cs->hw.mic.cfg_reg + MIC_ISAC;
207 cs->hw.mic.hscx = cs->hw.mic.cfg_reg + MIC_HSCX;
209 if (!request_region(cs->hw.mic.cfg_reg, bytecnt, "mic isdn")) {
212 cs->hw.mic.cfg_reg,
213 cs->hw.mic.cfg_reg + bytecnt);
217 cs->hw.mic.cfg_reg, c
[all...]
H A Dniccy.c133 ival = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG);
138 outl(ival, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG);
178 val = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG);
180 outl(val, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG);
181 release_region(cs->hw.niccy.cfg_reg, 0x40);
194 val = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG);
196 outl(val, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG);
282 cs->hw.niccy.cfg_reg = 0;
317 cs->hw.niccy.cfg_reg = pci_resource_start(niccy_dev, 0);
318 if (!cs->hw.niccy.cfg_reg) {
[all...]
H A Dsaphir.c176 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, 0xff);
179 if (cs->hw.saphir.cfg_reg)
180 release_region(cs->hw.saphir.cfg_reg, 6);
207 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, irq_val);
208 byteout(cs->hw.saphir.cfg_reg + RESET_REG, 1);
210 byteout(cs->hw.saphir.cfg_reg + RESET_REG, 0);
212 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, irq_val);
213 byteout(cs->hw.saphir.cfg_reg + SPARE_REG, 0x02);
255 cs->hw.saphir.cfg_reg = card->para[1];
260 if (!request_region(cs->hw.saphir.cfg_reg,
[all...]
H A Ddiva.c196 return (memreadreg(cs->hw.diva.cfg_reg, offset+0x80));
202 memwritereg(cs->hw.diva.cfg_reg, offset|0x80, value);
209 *data++ = memreadreg(cs->hw.diva.cfg_reg, 0x80);
216 memwritereg(cs->hw.diva.cfg_reg, 0x80, *data++);
222 return(memreadreg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0)));
228 memwritereg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0), value);
235 return (memreadreg(cs->hw.diva.cfg_reg, offset));
241 memwritereg(cs->hw.diva.cfg_reg, offset, value);
248 *data++ = memreadreg(cs->hw.diva.cfg_reg, 0);
255 memwritereg(cs->hw.diva.cfg_reg,
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/isdn/hisax/
H A Davm_a1p.c67 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_REG_OFFSET+offset);
68 ret = bytein(cs->hw.avm.cfg_reg+DATAREG_OFFSET);
76 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_REG_OFFSET+offset);
77 byteout(cs->hw.avm.cfg_reg+DATAREG_OFFSET, value);
83 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_FIFO_OFFSET);
84 insb(cs->hw.avm.cfg_reg+DATAREG_OFFSET, data, size);
90 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_FIFO_OFFSET);
91 outsb(cs->hw.avm.cfg_reg+DATAREG_OFFSET, data, size);
100 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,
102 ret = bytein(cs->hw.avm.cfg_reg
[all...]
H A Dteles3.c162 if (cs->hw.teles3.cfg_reg) {
164 release_region(cs->hw.teles3.cfg_reg, 1);
166 release_region(cs->hw.teles3.cfg_reg, 8);
179 if ((cs->hw.teles3.cfg_reg) && (cs->typ != ISDN_CTYPE_COMPAQ_ISA)) {
209 byteout(cs->hw.teles3.cfg_reg + 4, irqcfg);
211 byteout(cs->hw.teles3.cfg_reg + 4, irqcfg | 1);
214 byteout(cs->hw.teles3.cfg_reg, 0xff);
216 byteout(cs->hw.teles3.cfg_reg, 0x00);
331 cs->hw.teles3.cfg_reg = card->para[1];
332 switch (cs->hw.teles3.cfg_reg) {
[all...]
H A Ds0box.c98 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset));
104 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset, value);
110 read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size);
116 write_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size);
122 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset));
128 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset, value);
135 #define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg)
136 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg, data)
137 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscxfifo[nr], ptr, cnt)
138 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.teles3.cfg_reg, c
[all...]
H A Davm_a1.c110 while (((sval = bytein(cs->hw.avm.cfg_reg)) & 0xf) != 0x7) {
112 byteout(cs->hw.avm.cfg_reg, 0x1E);
113 sval = bytein(cs->hw.avm.cfg_reg);
140 release_region(cs->hw.avm.cfg_reg, 8);
169 byteout(cs->hw.avm.cfg_reg, 0x16);
170 byteout(cs->hw.avm.cfg_reg, 0x1E);
192 cs->hw.avm.cfg_reg = card->para[1] + 0x1800;
200 if (!request_region(cs->hw.avm.cfg_reg, 8, "avm cfg")) {
203 cs->hw.avm.cfg_reg,
204 cs->hw.avm.cfg_reg
[all...]
H A Dteles0.c187 if (cs->hw.teles0.cfg_reg)
188 release_region(cs->hw.teles0.cfg_reg, 8);
198 if (cs->hw.teles0.cfg_reg) {
229 byteout(cs->hw.teles0.cfg_reg + 4, cfval);
231 byteout(cs->hw.teles0.cfg_reg + 4, cfval | 1);
279 cs->hw.teles0.cfg_reg = card->para[2];
281 cs->hw.teles0.cfg_reg = 0;
290 if (cs->hw.teles0.cfg_reg) {
291 if (!request_region(cs->hw.teles0.cfg_reg, 8, "teles cfg")) {
295 cs->hw.teles0.cfg_reg,
[all...]
H A Dsportster.c129 bytein(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ +1);
139 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, 0);
141 adr = cs->hw.spt.cfg_reg + i *1024;
150 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq);
153 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq);
176 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq);
192 adr = cs->hw.spt.cfg_reg + i *1024;
204 adr = cs->hw.spt.cfg_reg + j *1024;
222 cs->hw.spt.cfg_reg = card->para[1];
226 cs->hw.spt.isac = cs->hw.spt.cfg_reg
[all...]
H A Dsedlbauer.c404 if (cs->hw.sedl.cfg_reg)
405 release_region(cs->hw.sedl.cfg_reg, bytecnt);
427 byteout(cs->hw.sedl.cfg_reg +3, cs->hw.sedl.reset_on);
429 byteout(cs->hw.sedl.cfg_reg +3, cs->hw.sedl.reset_off);
454 byteout(cs->hw.sedl.cfg_reg+ 5, 0);
474 byteout(cs->hw.sedl.cfg_reg+ 5, 0x02);
501 byteout(cs->hw.sedl.cfg_reg +3, cs->hw.sedl.reset_off);
512 byteout(cs->hw.sedl.cfg_reg +3, cs->hw.sedl.reset_off);
568 cs->hw.sedl.cfg_reg = card->para[1];
619 cs->hw.sedl.cfg_reg
[all...]
H A Davm_pci.c83 outb(idx, cs->hw.avm.cfg_reg + 4);
93 outb(idx, cs->hw.avm.cfg_reg + 4);
100 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4);
107 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4);
117 outl(idx, cs->hw.avm.cfg_reg + 4);
127 outl(idx, cs->hw.avm.cfg_reg + 4);
137 outb(idx, cs->hw.avm.cfg_reg + 4);
147 outb(idx, cs->hw.avm.cfg_reg + 4);
264 outl(idx, cs->hw.avm.cfg_reg + 4);
274 outb(idx, cs->hw.avm.cfg_reg
[all...]
H A Dmic.c163 if (cs->hw.mic.cfg_reg)
164 release_region(cs->hw.mic.cfg_reg, bytecnt);
203 cs->hw.mic.cfg_reg = card->para[1];
205 cs->hw.mic.adr = cs->hw.mic.cfg_reg + MIC_ADR;
206 cs->hw.mic.isac = cs->hw.mic.cfg_reg + MIC_ISAC;
207 cs->hw.mic.hscx = cs->hw.mic.cfg_reg + MIC_HSCX;
209 if (!request_region(cs->hw.mic.cfg_reg, bytecnt, "mic isdn")) {
212 cs->hw.mic.cfg_reg,
213 cs->hw.mic.cfg_reg + bytecnt);
217 cs->hw.mic.cfg_reg, c
[all...]
H A Dniccy.c133 ival = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG);
138 outl(ival, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG);
178 val = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG);
180 outl(val, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG);
181 release_region(cs->hw.niccy.cfg_reg, 0x40);
194 val = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG);
196 outl(val, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG);
282 cs->hw.niccy.cfg_reg = 0;
317 cs->hw.niccy.cfg_reg = pci_resource_start(niccy_dev, 0);
318 if (!cs->hw.niccy.cfg_reg) {
[all...]
H A Dsaphir.c176 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, 0xff);
179 if (cs->hw.saphir.cfg_reg)
180 release_region(cs->hw.saphir.cfg_reg, 6);
207 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, irq_val);
208 byteout(cs->hw.saphir.cfg_reg + RESET_REG, 1);
210 byteout(cs->hw.saphir.cfg_reg + RESET_REG, 0);
212 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, irq_val);
213 byteout(cs->hw.saphir.cfg_reg + SPARE_REG, 0x02);
255 cs->hw.saphir.cfg_reg = card->para[1];
260 if (!request_region(cs->hw.saphir.cfg_reg,
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/plat-omap/
H A Dmux.c40 || !arch_mux_cfg->cfg_reg) {
78 if (!mux_cfg->cfg_reg)
81 return mux_cfg->cfg_reg(reg);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-omap/
H A Dmux.c40 || !arch_mux_cfg->cfg_reg) {
78 if (!mux_cfg->cfg_reg)
81 return mux_cfg->cfg_reg(reg);

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