Searched refs:arch_sh2a_up (Results 1 - 6 of 6) sorted by relevance
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/bfd/ |
| H A D | cpu-sh.c | 363 { bfd_mach_sh2a, arch_sh2a, arch_sh2a_up },
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/bfd/ |
| H A D | cpu-sh.c | 363 { bfd_mach_sh2a, arch_sh2a, arch_sh2a_up },
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/bfd/ |
| H A D | cpu-sh.c | 363 { bfd_mach_sh2a, arch_sh2a, arch_sh2a_up },
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/opcodes/ |
| H A D | sh-opc.h | 333 | arch_sh2a_up)
357 | arch_sh2a_up \
359 #define arch_sh2a_up (arch_sh2a) macro
1095 {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32},
1097 {"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32},
1111 {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32},
1113 {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32},
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/opcodes/ |
| H A D | sh-opc.h | 333 | arch_sh2a_up)
357 | arch_sh2a_up \
359 #define arch_sh2a_up (arch_sh2a) macro
1095 {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32},
1097 {"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32},
1111 {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32},
1113 {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32},
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/opcodes/ |
| H A D | sh-opc.h | 333 | arch_sh2a_up)
357 | arch_sh2a_up \
359 #define arch_sh2a_up (arch_sh2a) macro
1095 {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32},
1097 {"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32},
1111 {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32},
1113 {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32},
|
Completed in 124 milliseconds