/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/opcodes/ |
H A D | ppc-opc.c | 1429 #define Z2_MASK ZRC (0x3f, 0xff, 1) 4467 { "dqua", ZRC(59,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4468 { "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4509 { "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4510 { "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4515 { "dquai", ZRC(59,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, 4516 { "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, 4521 { "drintx", ZRC(59,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 4522 { "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 4530 { "drintn", ZRC(59,227,0), Z2_MASK, POWER 1426 #define Z2_MASK macro [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/opcodes/ |
H A D | ppc-opc.c | 1429 #define Z2_MASK ZRC (0x3f, 0xff, 1) 4467 { "dqua", ZRC(59,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4468 { "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4509 { "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4510 { "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4515 { "dquai", ZRC(59,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, 4516 { "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, 4521 { "drintx", ZRC(59,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 4522 { "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 4530 { "drintn", ZRC(59,227,0), Z2_MASK, POWER 1426 #define Z2_MASK macro [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/opcodes/ |
H A D | ppc-opc.c | 1429 #define Z2_MASK ZRC (0x3f, 0xff, 1) 4467 { "dqua", ZRC(59,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4468 { "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4509 { "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4510 { "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4515 { "dquai", ZRC(59,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, 4516 { "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, 4521 { "drintx", ZRC(59,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 4522 { "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 4530 { "drintn", ZRC(59,227,0), Z2_MASK, POWER 1426 #define Z2_MASK macro [all...] |