Searched refs:XTALFREQ (Results 1 - 9 of 9) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/bcm97115/include/
H A Dbcm97115_uart.h2 #define XTALFREQ 8333333 macro
4 #define XTALFREQ 27000000 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/bcm9635x/include/
H A Dboard.h59 /* freq = (value + 1) * XTALFREQ/2 MHz */
72 #define XTALFREQ 25000000 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/scsi/
H A Dqlogicfas408.h30 #define XTALFREQ 40 macro
53 #define FASTCLK 0 /*(XTALFREQ>25?1:0)*/
57 /* This is the sync transfer divisor, XTALFREQ/X will be the maximum
60 #define SYNCXFRPD 5 /*(XTALFREQ/5)*/
H A Dqlogicfas408.c63 static int qlcfg5 = (XTALFREQ << 5); /* 15625/512 */
67 static int qlcfg9 = ((XTALFREQ + 4) / 5);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/scsi/
H A Dqlogicfas408.h30 #define XTALFREQ 40 macro
53 #define FASTCLK 0 /*(XTALFREQ>25?1:0)*/
57 /* This is the sync transfer divisor, XTALFREQ/X will be the maximum
60 #define SYNCXFRPD 5 /*(XTALFREQ/5)*/
H A Dqlogicfas408.c63 static int qlcfg5 = (XTALFREQ << 5); /* 15625/512 */
67 static int qlcfg9 = ((XTALFREQ + 4) / 5);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/bcm963xx/src/
H A Ddev_bcm63xx_uart.c12 #define XTALFREQ 25000000 macro
108 baudwd = (XTALFREQ / softc->baudrate) / 8;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/bcm97115/src/
H A Ddev_bcm7115_uart.c66 baudwd = (XTALFREQ / softc->baudrate) / 16;
H A Dbcm97115_init.S87 li t3, XTALFREQ / 115200 / 16

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