Searched refs:VSI0_CTL (Results 1 - 4 of 4) sorted by relevance
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/vme/bridges/ |
| H A D | vme_ca91cx42.h | 189 #define VSI0_CTL 0x0F00 macro
240 static const int CA91CX42_VSI_CTL[] = { VSI0_CTL, VSI1_CTL, VSI2_CTL, VSI3_CTL,
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| H A D | vme_ca91cx42.c | 1766 iowrite32(0x00F00000, bridge->base + VSI0_CTL);
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/vme/bridges/ |
| H A D | vme_ca91cx42.h | 189 #define VSI0_CTL 0x0F00 macro
240 static const int CA91CX42_VSI_CTL[] = { VSI0_CTL, VSI1_CTL, VSI2_CTL, VSI3_CTL,
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| H A D | vme_ca91cx42.c | 1766 iowrite32(0x00F00000, bridge->base + VSI0_CTL);
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