Searched refs:VBIT (Results 1 - 9 of 9) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/arm/
H A Darmsupp.c230 ASSIGNV ((state->Cpsr & VBIT) != 0);
231 state->Cpsr &= ~VBIT;
280 ASSIGNV ((state->Reg[15] & VBIT) != 0);
H A Darmemu.h48 #define VBIT (1L << 28) macro
185 ASSIGNV ((state->Reg[15] & VBIT) != 0); \
H A Darmemu.c3814 ASSIGNV ((temp & VBIT) != 0);
4820 ASSIGNV ((state->Reg[15] & VBIT) != 0);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/arm/
H A Darmsupp.c230 ASSIGNV ((state->Cpsr & VBIT) != 0);
231 state->Cpsr &= ~VBIT;
280 ASSIGNV ((state->Reg[15] & VBIT) != 0);
H A Darmemu.h48 #define VBIT (1L << 28) macro
185 ASSIGNV ((state->Reg[15] & VBIT) != 0); \
H A Darmemu.c3814 ASSIGNV ((temp & VBIT) != 0);
4820 ASSIGNV ((state->Reg[15] & VBIT) != 0);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/arm/
H A Darmsupp.c230 ASSIGNV ((state->Cpsr & VBIT) != 0);
231 state->Cpsr &= ~VBIT;
280 ASSIGNV ((state->Reg[15] & VBIT) != 0);
H A Darmemu.h48 #define VBIT (1L << 28) macro
185 ASSIGNV ((state->Reg[15] & VBIT) != 0); \
H A Darmemu.c3814 ASSIGNV ((temp & VBIT) != 0);
4820 ASSIGNV ((state->Reg[15] & VBIT) != 0);

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