Searched refs:ULPD_DPLL_CTRL (Results 1 - 6 of 6) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-omap1/
H A Dusb.c435 /* ULPD_DPLL_CTRL */
468 omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ));
474 w = omap_readw(ULPD_DPLL_CTRL);
476 omap_writew(w, ULPD_DPLL_CTRL);
482 while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
H A Dpm.c458 ULPD_SAVE(ULPD_DPLL_CTRL);
513 ULPD_SHOW(ULPD_DPLL_CTRL),
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-omap1/
H A Dusb.c435 /* ULPD_DPLL_CTRL */
468 omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ));
474 w = omap_readw(ULPD_DPLL_CTRL);
476 omap_writew(w, ULPD_DPLL_CTRL);
482 while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
H A Dpm.c458 ULPD_SAVE(ULPD_DPLL_CTRL);
513 ULPD_SHOW(ULPD_DPLL_CTRL),
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/plat-omap/include/plat/
H A Dhardware.h113 #define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-omap/include/plat/
H A Dhardware.h113 #define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c) macro

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