Searched refs:U300_SYSCON_CCR (Results 1 - 6 of 6) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-u300/
H A Dclock.c213 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
227 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
229 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
231 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
245 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
247 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
249 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
263 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
265 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
269 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
[all...]
H A Dcore.c1638 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1640 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-u300/
H A Dclock.c213 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
227 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
229 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
231 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
245 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
247 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
249 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
263 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
265 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
269 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
[all...]
H A Dcore.c1638 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1640 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-u300/include/mach/
H A Dsyscon.h23 #define U300_SYSCON_CCR (0x0000) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-u300/include/mach/
H A Dsyscon.h23 #define U300_SYSCON_CCR (0x0000) macro

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