Searched refs:TV_CTL (Results 1 - 6 of 6) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/gpu/drm/i915/
H A Dintel_tv.c914 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
919 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE);
1004 tv_ctl = I915_READ(TV_CTL);
1199 I915_WRITE(TV_CTL, tv_ctl);
1250 tv_ctl = I915_READ(TV_CTL);
1267 I915_WRITE(TV_CTL, tv_ctl);
1274 I915_WRITE(TV_CTL, save_tv_ctl);
1275 POSTING_READ(TV_CTL);
[all...]
H A Di915_reg.h1416 #define TV_CTL 0x68000 macro
1500 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/gpu/drm/i915/
H A Dintel_tv.c914 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
919 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE);
1004 tv_ctl = I915_READ(TV_CTL);
1199 I915_WRITE(TV_CTL, tv_ctl);
1250 tv_ctl = I915_READ(TV_CTL);
1267 I915_WRITE(TV_CTL, tv_ctl);
1274 I915_WRITE(TV_CTL, save_tv_ctl);
1275 POSTING_READ(TV_CTL);
[all...]
H A Di915_reg.h1416 #define TV_CTL 0x68000 macro
1500 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/video/
H A Dcyber2000fb.h400 #define TV_CTL 0xbe4dc /* reflects a previous register- MVFCLR, MVPCLR etc P241*/ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/video/
H A Dcyber2000fb.h400 #define TV_CTL 0xbe4dc /* reflects a previous register- MVFCLR, MVPCLR etc P241*/ macro

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