Searched refs:TLB_W (Results 1 - 4 of 4) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/powerpc/include/asm/
H A Dmmu-40x.h49 #define TLB_W 0x00000008 /* Caching is write-through */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/powerpc/include/asm/
H A Dmmu-40x.h49 #define TLB_W 0x00000008 /* Caching is write-through */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/microblaze/include/asm/
H A Dmmu.h107 # define TLB_W 0x00000008 /* Caching is write-through */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/microblaze/include/asm/
H A Dmmu.h107 # define TLB_W 0x00000008 /* Caching is write-through */ macro

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