Searched refs:TBIT (Results 1 - 12 of 12) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/opcodes/
H A Dia64-opc-i.c195 #define TBIT(a,b,c,d) \ macro
199 {"tbit.z", TBIT (0, 0, 0, 0)},
201 {"tbit.z.unc", TBIT (0, 0, 0, 1)},
203 {"tbit.z.and", TBIT (0, 1, 0, 0)},
205 {"tbit.nz.and", TBIT (0, 1, 0, 1)},
207 {"tbit.z.or", TBIT (1, 0, 0, 0)},
209 {"tbit.nz.or", TBIT (1, 0, 0, 1)},
211 {"tbit.z.or.andcm", TBIT (1, 1, 0, 0)},
213 {"tbit.nz.or.andcm", TBIT (1, 1, 0, 1)},
215 #undef TBIT macro
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/opcodes/
H A Dia64-opc-i.c195 #define TBIT(a,b,c,d) \ macro
199 {"tbit.z", TBIT (0, 0, 0, 0)},
201 {"tbit.z.unc", TBIT (0, 0, 0, 1)},
203 {"tbit.z.and", TBIT (0, 1, 0, 0)},
205 {"tbit.nz.and", TBIT (0, 1, 0, 1)},
207 {"tbit.z.or", TBIT (1, 0, 0, 0)},
209 {"tbit.nz.or", TBIT (1, 0, 0, 1)},
211 {"tbit.z.or.andcm", TBIT (1, 1, 0, 0)},
213 {"tbit.nz.or.andcm", TBIT (1, 1, 0, 1)},
215 #undef TBIT macro
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/opcodes/
H A Dia64-opc-i.c195 #define TBIT(a,b,c,d) \ macro
199 {"tbit.z", TBIT (0, 0, 0, 0)},
201 {"tbit.z.unc", TBIT (0, 0, 0, 1)},
203 {"tbit.z.and", TBIT (0, 1, 0, 0)},
205 {"tbit.nz.and", TBIT (0, 1, 0, 1)},
207 {"tbit.z.or", TBIT (1, 0, 0, 0)},
209 {"tbit.nz.or", TBIT (1, 0, 0, 1)},
211 {"tbit.z.or.andcm", TBIT (1, 1, 0, 0)},
213 {"tbit.nz.or.andcm", TBIT (1, 1, 0, 1)},
215 #undef TBIT macro
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/arm/
H A Darmemu.h63 #define TBIT (1L << 5) macro
201 ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \
H A Darmsupp.c235 ASSIGNT ((state->Cpsr & TBIT) != 0);
236 state->Cpsr &= ~TBIT;
H A Darmemu.c1692 /* Don't allow TBIT to be set by MSR. */
1693 temp &= ~ TBIT;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/arm/
H A Darmemu.h63 #define TBIT (1L << 5) macro
201 ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \
H A Darmsupp.c235 ASSIGNT ((state->Cpsr & TBIT) != 0);
236 state->Cpsr &= ~TBIT;
H A Darmemu.c1692 /* Don't allow TBIT to be set by MSR. */
1693 temp &= ~ TBIT;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/arm/
H A Darmemu.h63 #define TBIT (1L << 5) macro
201 ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \
H A Darmsupp.c235 ASSIGNT ((state->Cpsr & TBIT) != 0);
236 state->Cpsr &= ~TBIT;
H A Darmemu.c1692 /* Don't allow TBIT to be set by MSR. */
1693 temp &= ~ TBIT;

Completed in 212 milliseconds