Searched refs:SVC (Results 1 - 13 of 13) sorted by relevance
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/kernel/ |
| H A D | entry-header.S | 50 @ available. Should only be called from SVC mode
61 msr cpsr_c, \rtemp @ switch back to the SVC mode
73 msr cpsr_c, \rtemp @ switch back to the SVC mode
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| H A D | entry-armv.S | 118 * SVC mode handlers
297 ldr r2, [sp, #S_PSR] @ Get SVC cpsr
1044 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1080 movs pc, lr @ branch to handler in SVC mode
1160 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1187 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/kernel/ |
| H A D | entry-header.S | 50 @ available. Should only be called from SVC mode
61 msr cpsr_c, \rtemp @ switch back to the SVC mode
73 msr cpsr_c, \rtemp @ switch back to the SVC mode
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| H A D | entry-armv.S | 118 * SVC mode handlers
297 ldr r2, [sp, #S_PSR] @ Get SVC cpsr
1044 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1080 movs pc, lr @ branch to handler in SVC mode
1160 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1187 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-sa1100/ |
| H A D | sleep.S | 163 msr cpsr_c, r0 @ set SVC, irqs off
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-sa1100/ |
| H A D | sleep.S | 163 msr cpsr_c, r0 @ set SVC, irqs off
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-pxa/ |
| H A D | sleep.S | 104 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off
331 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-pxa/ |
| H A D | sleep.S | 104 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off
331 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/opcodes/ |
| H A D | i370-opc.c | 113 /* The I field in an RR form SVC-style instruction. */
304 /* An SVC-style instruction. */
305 #define SVC(op, i) \
308 #define SVC_MASK SVC (0xff, 0x0)
545 { "svc", 2, {{SVC(0x0a,0), 0}}, {{SVC_MASK, 0}}, I370, {RR_I} },
301 #define SVC macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/opcodes/ |
| H A D | i370-opc.c | 113 /* The I field in an RR form SVC-style instruction. */
304 /* An SVC-style instruction. */
305 #define SVC(op, i) \
308 #define SVC_MASK SVC (0xff, 0x0)
545 { "svc", 2, {{SVC(0x0a,0), 0}}, {{SVC_MASK, 0}}, I370, {RR_I} },
301 #define SVC macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/opcodes/ |
| H A D | i370-opc.c | 113 /* The I field in an RR form SVC-style instruction. */
304 /* An SVC-style instruction. */
305 #define SVC(op, i) \
308 #define SVC_MASK SVC (0xff, 0x0)
545 { "svc", 2, {{SVC(0x0a,0), 0}}, {{SVC_MASK, 0}}, I370, {RR_I} },
301 #define SVC macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mm/ |
| H A D | proc-xscale.S | 505 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mm/ |
| H A D | proc-xscale.S | 505 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
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