Searched refs:SSCR1_SPO (Results 1 - 6 of 6) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/plat-pxa/include/plat/
H A Dssp.h71 #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-pxa/include/plat/
H A Dssp.h71 #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h772 #define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ macro
773 #define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */
774 #define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h772 #define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ macro
773 #define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */
774 #define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/spi/
H A Dpxa2xx_spi.c62 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
71 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
1313 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1315 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/spi/
H A Dpxa2xx_spi.c62 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
71 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
1313 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1315 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);

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