Searched refs:SMCR (Results 1 - 4 of 4) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/i2c/busses/
H A Di2c-highlander.c24 #define SMCR 0x00 macro
60 iowrite16(ioread16(dev->base + SMCR) | SMCR_IEIC, dev->base + SMCR);
65 iowrite16(ioread16(dev->base + SMCR) & ~SMCR_IEIC, dev->base + SMCR);
70 iowrite16(ioread16(dev->base + SMCR) | SMCR_START, dev->base + SMCR);
75 iowrite16(ioread16(dev->base + SMCR) | SMCR_IRIC, dev->base + SMCR);
134 while (ioread16(dev->base + SMCR)
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/i2c/busses/
H A Di2c-highlander.c24 #define SMCR 0x00 macro
60 iowrite16(ioread16(dev->base + SMCR) | SMCR_IEIC, dev->base + SMCR);
65 iowrite16(ioread16(dev->base + SMCR) & ~SMCR_IEIC, dev->base + SMCR);
70 iowrite16(ioread16(dev->base + SMCR) | SMCR_START, dev->base + SMCR);
75 iowrite16(ioread16(dev->base + SMCR) | SMCR_IRIC, dev->base + SMCR);
134 while (ioread16(dev->base + SMCR)
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-sa1100/include/mach/
H A DSA-1101.h80 * SMCR Shared Memory Controller Register
90 #define SMCR (*((volatile Word *) SA1101_p2v (_SMCR))) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-sa1100/include/mach/
H A DSA-1101.h80 * SMCR Shared Memory Controller Register
90 #define SMCR (*((volatile Word *) SA1101_p2v (_SMCR))) macro

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