/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/opcodes/ |
H A D | m10300-opc.c | 180 #define SIMM8 (SD8N_SHIFT8+1) 184 #define SIMM16 (SIMM8+1) 451 { "mov", 0x8000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}}, 532 { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, 533 { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, 567 { "mov", 0xfb080000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 594 { "mac", 0xfb0b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 604 { "macb", 0xfb2b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 614 { "mach", 0xfb4b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 733 { "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN 179 #define SIMM8 macro [all...] |
H A D | m10200-opc.c | 121 #define SIMM8 (SD8N_PCREL+1) 125 #define SIMM16 (SIMM8+1) 167 { "mov", 0x8000, 0xf000, FMT_2, {SIMM8, DN01}}, 247 { "add", 0xd400, 0xfc00, FMT_2, {SIMM8, DN0}}, 250 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}}, 254 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}}, 275 { "cmp", 0xd800, 0xfc00, FMT_2, {SIMM8, DN0}}, 120 #define SIMM8 macro
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H A D | m32r-opinst.c | 78 { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 }, 291 { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
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H A D | m32r-opc.c | 285 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, 633 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, 1628 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
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H A D | mep-opc.c | 673 { { MNEM, ' ', OP (RN), ',', OP (SIMM8), 0 } },
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/opcodes/ |
H A D | m10300-opc.c | 180 #define SIMM8 (SD8N_SHIFT8+1) 184 #define SIMM16 (SIMM8+1) 451 { "mov", 0x8000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}}, 532 { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, 533 { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, 567 { "mov", 0xfb080000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 594 { "mac", 0xfb0b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 604 { "macb", 0xfb2b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 614 { "mach", 0xfb4b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 733 { "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN 179 #define SIMM8 macro [all...] |
H A D | m10200-opc.c | 121 #define SIMM8 (SD8N_PCREL+1) 125 #define SIMM16 (SIMM8+1) 167 { "mov", 0x8000, 0xf000, FMT_2, {SIMM8, DN01}}, 247 { "add", 0xd400, 0xfc00, FMT_2, {SIMM8, DN0}}, 250 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}}, 254 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}}, 275 { "cmp", 0xd800, 0xfc00, FMT_2, {SIMM8, DN0}}, 120 #define SIMM8 macro
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H A D | m32r-opinst.c | 78 { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 }, 291 { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
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H A D | m32r-opc.c | 285 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, 633 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, 1628 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
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H A D | mep-opc.c | 673 { { MNEM, ' ', OP (RN), ',', OP (SIMM8), 0 } },
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/opcodes/ |
H A D | m10300-opc.c | 180 #define SIMM8 (SD8N_SHIFT8+1) 184 #define SIMM16 (SIMM8+1) 451 { "mov", 0x8000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}}, 532 { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, 533 { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, 567 { "mov", 0xfb080000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 594 { "mac", 0xfb0b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 604 { "macb", 0xfb2b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 614 { "mach", 0xfb4b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 733 { "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN 179 #define SIMM8 macro [all...] |
H A D | m10200-opc.c | 121 #define SIMM8 (SD8N_PCREL+1) 125 #define SIMM16 (SIMM8+1) 167 { "mov", 0x8000, 0xf000, FMT_2, {SIMM8, DN01}}, 247 { "add", 0xd400, 0xfc00, FMT_2, {SIMM8, DN0}}, 250 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}}, 254 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}}, 275 { "cmp", 0xd800, 0xfc00, FMT_2, {SIMM8, DN0}}, 120 #define SIMM8 macro
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H A D | m32r-opinst.c | 78 { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 }, 291 { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
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H A D | m32r-opc.c | 285 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, 633 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, 1628 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
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H A D | mep-opc.c | 673 { { MNEM, ' ', OP (RN), ',', OP (SIMM8), 0 } },
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mn10300/mm/ |
H A D | misalignment.c | 123 SIMM8, /* 8-bit signed immediate */ enumerator in enum:value_id 216 { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, 217 { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, 273 { "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, 274 { "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, 624 case SIMM8:
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mn10300/mm/ |
H A D | misalignment.c | 123 SIMM8, /* 8-bit signed immediate */ enumerator in enum:value_id 216 { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, 217 { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, 273 { "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, 274 { "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, 624 case SIMM8:
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