Searched refs:SD8N_SHIFT8 (Results 1 - 3 of 3) sorted by relevance
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/opcodes/ |
| H A D | m10300-opc.c | 176 #define SD8N_SHIFT8 (SD8N_PCREL+1)
180 #define SIMM8 (SD8N_SHIFT8+1)
893 /* Place these before the ones with IMM8E and SD8N_SHIFT8 since we want the
900 { "btst", 0xfaf80000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
905 { "bset", 0xfaf00000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
910 { "bclr", 0xfaf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
175 #define SD8N_SHIFT8 macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/opcodes/ |
| H A D | m10300-opc.c | 176 #define SD8N_SHIFT8 (SD8N_PCREL+1)
180 #define SIMM8 (SD8N_SHIFT8+1)
893 /* Place these before the ones with IMM8E and SD8N_SHIFT8 since we want the
900 { "btst", 0xfaf80000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
905 { "bset", 0xfaf00000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
910 { "bclr", 0xfaf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
175 #define SD8N_SHIFT8 macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/opcodes/ |
| H A D | m10300-opc.c | 176 #define SD8N_SHIFT8 (SD8N_PCREL+1)
180 #define SIMM8 (SD8N_SHIFT8+1)
893 /* Place these before the ones with IMM8E and SD8N_SHIFT8 since we want the
900 { "btst", 0xfaf80000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
905 { "bset", 0xfaf00000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
910 { "bclr", 0xfaf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
175 #define SD8N_SHIFT8 macro
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