Searched refs:S5P_CLK_SRC2 (Results 1 - 10 of 10) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pc100/include/mach/
H A Dregs-clock.h34 #define S5P_CLK_SRC2 S5P_CLKREG(0x208) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pc100/include/mach/
H A Dregs-clock.h34 #define S5P_CLK_SRC2 S5P_CLKREG(0x208) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5p6442/include/mach/
H A Dregs-clock.h32 #define S5P_CLK_SRC2 S5P_CLKREG(0x208) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pc100/
H A Dclock.c1001 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
1044 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
1055 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
1066 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
1077 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
1088 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1099 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1110 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1121 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5p6442/include/mach/
H A Dregs-clock.h32 #define S5P_CLK_SRC2 S5P_CLKREG(0x208) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pc100/
H A Dclock.c1001 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
1044 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
1055 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
1066 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
1077 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
1088 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1099 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1110 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1121 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pv210/include/mach/
H A Dregs-clock.h32 #define S5P_CLK_SRC2 S5P_CLKREG(0x208) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pv210/include/mach/
H A Dregs-clock.h32 #define S5P_CLK_SRC2 S5P_CLKREG(0x208) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pv210/
H A Dclock.c863 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
873 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
883 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pv210/
H A Dclock.c863 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
873 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
883 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },

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